IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2022/03/07)

Presentation

[Memorial Lecture] An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers

Lingxiao Hou(Nagoya Univ.), Yutaka Masuda(Nagoya Univ.), Tohru Ishihara(Nagoya Univ.),

[Date]2022-03-07
[Paper #]VLD2021-83,HWS2021-60

A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis

Koyu Ohata(Ritsumeikan Univ.), Hiroki Nishikawa(Ritsumeikan Univ.), Xiangbo Kong(Ritsumeikan Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2022-03-07
[Paper #]VLD2021-78,HWS2021-55

A Force-Haptic Guided Control System for Smooth Manipulation of Flexible Objects by Teleoperated Robots

Satoko Iida(Kyoto Univ.), Hiromitu Awano(Kyoto Univ.),

[Date]2022-03-07
[Paper #]VLD2021-89,HWS2021-66

AmoebaSAT-based Efficient Accelerator for Autonomous Driving Application

Yusuke Inuma(Tokyo Tech), Yuko Hara-Azumi(Tokyo Tech),

[Date]2022-03-07
[Paper #]VLD2021-90,HWS2021-67

Measurement Results of Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations

Yuki Abe(KIT), Kazutoshi Kobayashi(KIT), Hiroyuki Ochi(Ritsumeikan Univ.),

[Date]2022-03-07
[Paper #]VLD2021-85,HWS2021-62

[Memorial Lecture] DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification

Dehua Liang(Osaka Univ.), Jun Shiomi(Osaka Univ.), Noriyuki Miura(Osaka Univ.), Hiromitsu Awano(Kyoto Univ.),

[Date]2022-03-07
[Paper #]VLD2021-84,HWS2021-61

Bottleneck Channel Routing to Reduce the Area of Analog VLSI

Kazuya Taniguchi(Tokyo Tech), Satoshi Tayu(Tokyo Tech), Atsushi Takahashi(Tokyo Tech), Yukichi Todoroki(Jedat), Makoto Minami(Jedat),

[Date]2022-03-07
[Paper #]VLD2021-77,HWS2021-54

Attribute-based Encryption Acceleration by Pairing Engine Hardware on FPGA

Anawin Opasatian(EEIS, The University of Tokyo), Makoto Ikeda(EEIS, The University of Tokyo),

[Date]2022-03-07
[Paper #]VLD2021-80,HWS2021-57

Design and Measurement of Crypto Processor for Post Quantum Cryptography CRYSTALS-Kyber

Taishin Shimada(Univ. of Tokyo), Makoto Ikeda(Univ. of Tokyo),

[Date]2022-03-07
[Paper #]VLD2021-81,HWS2021-58

An efficient scheme of homomorphic encryption for stochastic computing and its performance evaluation

Ryusuke Koseki(Tohoku Univ.), Rei Ueno(Tohoku Univ.), Akira Ito(Tohoku Univ.), Naofumi Homma(Tohoku Univ.),

[Date]2022-03-07
[Paper #]VLD2021-82,HWS2021-59

High-throughput In-Memory Accelerator for Binarized Neural Network based on 8T-SRAM

Hiroto Tagata(Kyoto Univ.), Hiromitsu Awano(Kyoto Univ.),

[Date]2022-03-07
[Paper #]VLD2021-88,HWS2021-65

Low-Energy and Fast Inference Method for Spiking Neural Networks Using Dynamic Threshold Adjustment

Takehiro Habara(Kyoto Univ.), Hiromitsu Awano(Kyoto Univ.),

[Date]2022-03-07
[Paper #]VLD2021-87,HWS2021-64

MTJ-based non-volatile SRAM circuit with Approximate Image-data Storing for energy saving

Hisato Miyauchi(SIT), Kimiyoshi Usami(SIT),

[Date]2022-03-07
[Paper #]VLD2021-86,HWS2021-63

Improved placement-method of standard cells considering parallel routing

Takeru Furuyashiki(TUAT), Kunihiro Fujiyoshi(TUAT),

[Date]2022-03-07
[Paper #]VLD2021-76,HWS2021-53

Datapath Synthesis Considering Temperature Dependent Timing Skew

Mineo Kaneko(JAIST),

[Date]2022-03-07
[Paper #]VLD2021-79,HWS2021-56

Evaluation of Side-channel Leaks Specific to Unrolled AES Hardware

Ayano Nakashima(Tohoku Univ.), Rei Ueno(Tohoku Univ.), Naofumi Homma(Tohoku Univ.),

[Date]2022-03-08
[Paper #]VLD2021-100,HWS2021-77

Bypassing Isolated Execution on RISC-V Keystone using Fault Injection

Shoei Nashimoto(Mitsubishi Electric), Daisuke Suzuki(Mitsubishi Electric), Rei Ueno(Tohoku Univ.), Naofumi Homma(Tohoku Univ.),

[Date]2022-03-08
[Paper #]VLD2021-101,HWS2021-78

Evaluation of a Lightweight Cryptographic Finalist on SROS2

Shu Takemoto(Meijo Univ.), Yoshiya Ikezaki(Meijo Univ.), Yusuke Nozaki(Meijo Univ.), Masaya Yoshikawa(Meijo Univ.),

[Date]2022-03-08
[Paper #]VLD2021-94,HWS2021-71

Implementation Evaluation of Glitch PUF Using a Low-Latency Cryptography MANTIS

Kosuke Hamaguchi(Meijo Univ.), Shu Takemoto(Meijo Univ.), Yusuke Nozaki(Meijo Univ.), Masaya Yoshikawa(Meijo Univ.),

[Date]2022-03-08
[Paper #]VLD2021-96,HWS2021-73

Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment

Takuma Nagao(National Institute of Technology (KOSEN)), Michihiro Shintani(Nara Institute of Science and Technology), Ken'ichi Yamaguchi(National Institute of Technology (KOSEN)), Hiroshi Iwata(National Institute of Technology (KOSEN)), Tomoki Nakamura(SCK), Masuo Kajiyama(SCK), Makoto Eiki(SCK), Michiko Inoue(Nara Institute of Science and Technology),

[Date]2022-03-08
[Paper #]VLD2021-92,HWS2021-69