IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2018/02/28)

Presentation

A Study of Acceleration Optimization for an EV Cart with a Lithium-ion Battery

Haruya Fujii(Ritsumeikan Univ.), Yoshiki Tsuchida(Ritsumeikan Univ.), Tomoki Abe(Ritsumeikan Univ.), Lei Lin(Ritsumeikan Univ.), Masahiro Fukui(Ritsumeikan Univ.),

[Date]2018-02-28
[Paper #]VLD2017-100

Congestion Aware High Level Synthesis Design Flow with Source Compiler

Masato Tatsuoka(JAIST), Mineo Kaneko(JAIST),

[Date]2018-02-28
[Paper #]VLD2017-96

Random Testing of Android Virtual Machine by Valid Dex File Generation

Hirofumi Ikeo(Kwansei Gakuin Univ.), Ryotaro Shimizu(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2018-02-28
[Paper #]VLD2017-95

Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes

Haruki Maruoka(KIT), Kodai Yamada(KIT), Mitsunori Ebara(KIT), Jun Furuta(KIT), Kazutoshi Kobayashi(KIT),

[Date]2018-02-28
[Paper #]VLD2017-103

Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage

Mitsunori Ebara(KIT), Haruki Maruoka(KIT), Kodai Yamada(KIT), Jun Furuta(KIT), Kazutoshi Kobayashi(KIT),

[Date]2018-02-28
[Paper #]VLD2017-104

Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis

Daisuke Ishikawa(TCU), Kenshu Seto(TCU),

[Date]2018-02-28
[Paper #]VLD2017-97

On Memory Size Reduction of Programmable Hardware for Random Forest based Network Intrusion Detection

Binbin Xue(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.),

[Date]2018-02-28
[Paper #]VLD2017-90

k-Nearest Neighbor Search Hardware Using Locality Sensitive Hashing for High-Dimensional Data

Yuto Arai(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.),

[Date]2018-02-28
[Paper #]VLD2017-91

Systematic Analysis Framework of Variables Significance towards Approximate Computing

Sara Ayman Metwalli(Tokyo Tech), Yuko Hara-Azumi(Tokyo Tech),

[Date]2018-02-28
[Paper #]VLD2017-94

Amoeba-inspired SAT Solvers on FPGA through High Level Synthesis

Hoang Ngoc Anh Nguyen(Tokyo Tech), Masashi Aono(Keio Univ.), Yuko Hara-Azumi(Tokyo Tech),

[Date]2018-02-28
[Paper #]VLD2017-93

A fast routing method for multi-terminal nets using constraint satisfaction problem

Saki Yamaguchi(Univ. of Kitakyushu), Yasuhiro Takashima(Univ. of Kitakyushu),

[Date]2018-02-28
[Paper #]VLD2017-92

Architecture of Full-HD 60-fps Real-time Optical Flow Processor

Satoshi Kanda(Nihon Univ.), Kousuke Imamura(Kanazawa Univ.), Yoshio Matsuda(Kanazawa Univ.), Tetsuya Matsumura(Nihon Univ.),

[Date]2018-02-28
[Paper #]VLD2017-99

On Fast Computation of RBF Approximate Function by FPGA Implementation

Shogo Masuda(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.),

[Date]2018-02-28
[Paper #]VLD2017-89

Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults

Cheng Ma(JAIST), Mineo Kaneko(JAIST),

[Date]2018-02-28
[Paper #]VLD2017-101

Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths

Junghoon Oh(JAIST), Mineo Kaneko(JAIST),

[Date]2018-02-28
[Paper #]VLD2017-102

A Study on Quality Improvement of Frame Interpolation Method with High-Resolution and High-Frame Rate Video Using Foreground Elimination and Contour Extraction

Hirofumi Ihara(Ritumeikan Univ), Takashi Imagawa(Ritumeikan Univ), Hiroki Uesaka(Hokkaido Univ), Shingo Kokami(Hokkaido Univ), Hiroshi Tsutsui(Hokkaido Univ), Yoshikazu Miyanaga(Hokkaido Univ), Hiroyuki Ochi(Ritumeikan Univ),

[Date]2018-02-28
[Paper #]VLD2017-98

Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning

Kota Muroi(Univ. of Aizu), Yukihide Kohira(Univ. of Aizu),

[Date]2018-03-01
[Paper #]VLD2017-107

Hardware/Software co-design environment in model-based parallelization (MBP)

Kazuki Kashiwabara(Nagoya Univ.), Shinya Honda(Nagoya Univ.), Masato Edahiro(Nagoya Univ.),

[Date]2018-03-01
[Paper #]VLD2017-115

A SW/HW Partitioning for Model Based Design

Ryo Yamamoto(Mitsubishi Electric), Koki Murano(Mitsubishi Electric), Ayumu Yamamoto(Mitsubishi Electric), Yoshihiro Ogawa(Mitsubishi Electric),

[Date]2018-03-01
[Paper #]VLD2017-113

Efficient Generation of Lithography Hotspot Detector based on Transfer Learning

Shuhei Suzuki(UoA), Yoichi Tomioka(UoA),

[Date]2018-03-01
[Paper #]VLD2017-106