IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2017/03/01)

Presentation

Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines

Shota Enokido(SIT), Kimiyoshi Usami(SIT),

[Date]2017-03-01
[Paper #]VLD2016-102

Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models

Shogo Senba(UoA), Hiroshi Saito(UoA),

[Date]2017-03-01
[Paper #]VLD2016-107

Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement

Hayato Mashiko(Univ. of Aizu), Yukihide Kohira(Univ. of Aizu),

[Date]2017-03-01
[Paper #]VLD2016-104

A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating

Masaru Kudo(Shibaura Institute of Tech.), Kimiyoshi Usami(Shibaura Institute of Tech.),

[Date]2017-03-01
[Paper #]VLD2016-103

High accuracy 8*8 approximate multiplier based on OR operation

Yi Guo(Waseda Univ.), Heming Sun(Waseda Univ.), Canran Jin(Waseda Univ.), Shinji Kimura(Waseda Univ.),

[Date]2017-03-01
[Paper #]VLD2016-105

A Design Technique for Approximate Circuits based on Artificial Neural Network

Kazushi Kawamura(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2017-03-01
[Paper #]VLD2016-106

FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration

Naoyuki Miyagawa(Ritsumeikan Univ.), Tomoya Kimura(Ritsumeikan Univ.), Hiroyuki Ochi(Ritsumeikan Univ.),

[Date]2017-03-02
[Paper #]VLD2016-109

[Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture

Yuki Kobayashi(NEC), Yoshikazu Watanabe(NEC), Seiya Shibata(NEC), Takashi Takenaka(NEC), Takeo Hosomi(NEC), Yuichi Nakamura(NEC),

[Date]2017-03-02
[Paper #]VLD2016-115

[Invited Talk] IP Timing Constraints Promotion Challenges

Tatsuya Nakae(Socionext), Ichiro Shiihara(Socionext),

[Date]2017-03-02
[Paper #]VLD2016-116

Optimum Temperature Dependent Timing Skew for Temperature Aware Design

Makoto Soga(JAIST), Mineo Kaneko(JAIST),

[Date]2017-03-02
[Paper #]VLD2016-119

MILP Approach to Skew-Aware High Level Synthesis

Kai Shimura(JAIST), Mineo Kaneko(JAIST),

[Date]2017-03-02
[Paper #]VLD2016-120

High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering

Shohei Handa(Tokyo TECH), Shimpei Sato(Tokyo TECH), Atsushi Takahashi(Tokyo TECH),

[Date]2017-03-02
[Paper #]VLD2016-111

Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning

Atsushi Ogashira(Tokyo TECH), Shimpei Sato(Tokyo TECH), Atsushi Takahashi(Tokyo TECH),

[Date]2017-03-02
[Paper #]VLD2016-113

An algorithm to compute covariance for finding distribution of the maximum

Daiki Azuma(Chuo Univ.), Shuji Tsukiyama(Chuo Univ.), Masahiro Fukui(Ritsumeikan Univ.), Takashi Kambe(Kinki Univ.),

[Date]2017-03-02
[Paper #]VLD2016-121

Acceleration of a Hotspot Detection Method Based on Approximate String Matching for LSI Mask Pattern Using Table Reference

Shuma Tamagawa(Hirohima City Univ.), Masato Inagi(Hirohima City Univ.), Shinobu Nagayama(Hirohima City Univ.), Shin'ichi Wakabayashi(Hirohima City Univ.),

[Date]2017-03-02
[Paper #]VLD2016-112

[Invited Talk] Fast Monte Carlo based timing yield calculation via line sampling

Hiromitsu Awano(UTokyo), Takashi Sato(Kyoto Univ.),

[Date]2017-03-02
[Paper #]VLD2016-117

Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing

Shun Sugihara(Tokyo Tech), Shimpei Sato(Tokyo Tech), Atsushi Takahashi(Tokyo Tech),

[Date]2017-03-02
[Paper #]VLD2016-114

Reliability enhancement of Hierarchical data reading circuit of Wafer scale mask ROM

Takaaki Yokoyama(Ritsumeikan Univ), Ochi Hiroyuki(Ritsumeikan Univ),

[Date]2017-03-02
[Paper #]VLD2016-110

Generation of Optimum Screening Patterns for a Screening Circuit to Detect Network Intrusion

Tomoaki Hashimoto(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.),

[Date]2017-03-02
[Paper #]VLD2016-108

Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis

Xiaoguang Li(JAIST), Mineo Kaneko(JAIST),

[Date]2017-03-02
[Paper #]VLD2016-118