IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2016/02/29)

Presentation

Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation

Kazuhiro Nakamura(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2016-02-29
[Paper #]VLD2015-112

Tool Support for Verifying Large Scale Hardware Design with Verilog-HDL

Yuta Morimitsu(Okayama Prefectural Univ.), Tomoyuki Yokogawa(Okayama Prefectural Univ.), Masafumi Kondo(Kawasaki Univ. of Medical Welfare), Hisashi Miyazaki(Kawasaki Univ. of Medical Welfare), Yoichiro Sato(Okayama Prefectural Univ.), Kazutami Arimoto(Okayama Prefectural Univ.), Norihiro Yoshida(Nagoya Univ.),

[Date]2016-02-29
[Paper #]VLD2015-111

High-Level Synthesis of Embedded Systems Controller from Erlang

Hinata Takabeyashi(Kwansei Gakuin Univ), Nagisa Ishiura(Kwansei Gakuin Univ), Kagumi Azuma(Kwansei Gakuin Univ), Nobuaki Yoshida(ASTEM), Hiroyuki Kanbara(ASTEM),

[Date]2016-02-29
[Paper #]VLD2015-114

ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components

Junghoon Oh(JAIST), Mineo Kaneko(JAIST),

[Date]2016-02-29
[Paper #]VLD2015-116

Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme

Hiroshi Saito(Univ. Aizu), Masashi Imai(Hirosaki Univ.), Tomohiro Yoneda(NII),

[Date]2016-02-29
[Paper #]VLD2015-113

A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis

Keisuke Inoue(KTC), Mineo Kaneko(JAIST),

[Date]2016-02-29
[Paper #]VLD2015-117

A Multi-Paradigm High-Level Hardware Design Environment

Shinya Takamaeda(NAIST),

[Date]2016-02-29
[Paper #]VLD2015-115

Electromagnetic Analysis Attack for Simeck and Simon

Yusuke Nozaki(Meijo Univ.), Masaya Yoshikawa(Meijo Univ.),

[Date]2016-03-01
[Paper #]VLD2015-121

IP Design using High-Level Synthesis Design Flow

Masato Tatsuoka(SNI), Ken Imanishi(SNI), Hidenori Nakaishi(SNI), Takeshi Toyoyama(SNI),

[Date]2016-03-01
[Paper #]VLD2015-126

Power Analysis Attack for Countermeasure with Check Circuit

Yoshiya Ikezaki(Meijo Univ.), Masaya Yoshikawa(Meijo Univ.),

[Date]2016-03-01
[Paper #]VLD2015-122

Noise reduction effect for input dependence of Zigzag Power Gating

Tadahiro Kanamoto(Shibaura Institute of Tech.), Kimiyoshi Usami(Shibaura Institute of Tech.),

[Date]2016-03-01
[Paper #]VLD2015-128

A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search

Yoshifumi Kawamura(Kanazawa Univ.), Kousuke Imamura(Kanazawa Univ.), Naoki Miura(NTT), Masami Urano(NTT), Satoshi Shigematsu(NTT), Tetsuya Matsumura(Nihon Univ.), Yoshio Matsuda(Kanazawa Univ.),

[Date]2016-03-01
[Paper #]VLD2015-118

Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX.

Hanano Suzuki(Shibaura IT), Kimiyoshi Usami(Shibaura IT),

[Date]2016-03-01
[Paper #]VLD2015-129

FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis

Koichi Fujiwara(Waseda Univ.), Kawamura Kazushi(Waseda Univ.), Keita Igarashi(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2016-03-01
[Paper #]VLD2015-127

Timing-error-tolerant AES Cipher

Shinnosuke Yoshida(Waseda Univ.), Youhua Shi(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2016-03-01
[Paper #]VLD2015-123

Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control

Yusuke Yoshida(SIT), Masaru Kudo(SIT), Kimiyoshi Usami(SIT),

[Date]2016-03-01
[Paper #]VLD2015-130

Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors

Koki Ito(Waseda Univ.), Kazushi Kawamura(Waseda Univ.), Yutaka Tamiya(Fujitsu Lab.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2016-03-01
[Paper #]VLD2015-120

A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation

Hiroki Takaguchi(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.),

[Date]2016-03-01
[Paper #]VLD2015-119

[Memorial Lecture] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region

Tatsuya Kamakari(Kyoto Univ.), Jun Shiomi(Kyoto Univ.), Tohru Ishihara(Kyoto Univ.), Hidetoshi Onodera(Kyoto Univ.),

[Date]2016-03-01
[Paper #]VLD2015-131

[Invited Talk] VLSI Technology for Embedded Systems in the More than Moore Era

Masaharu Imai(Osaka Univ.), Yoshinori Takeuchi(Osaka Univ.),

[Date]2016-03-01
[Paper #]VLD2015-125