Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2015/02/23)

Presentation
表紙

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[Date]2015/2/23
[Paper #]
目次

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[Date]2015/2/23
[Paper #]
A Fast Lithographic Mask Correction Algorithm

Ahmed Awad,  Atsushi Takahashi,  

[Date]2015/2/23
[Paper #]VLD2014-153
A cut-pattern reduction method for routing in Self-Aligned Double Patterning

Noriyuki TAKAHASHI,  Takeshi IHARA,  Atsushi TAKAHASHI,  

[Date]2015/2/23
[Paper #]VLD2014-154
Faster Numberlink solution using possibilities of topological routing

Yuichiro TANAKA,  Atsushi TAKAHASHI,  

[Date]2015/2/23
[Paper #]VLD2014-155
Zero-weighted Cycle Finding Method for Exchanging Pin Pair on Set-Pair Rouitng

Yuta NAKATANI,  Atsushi TAKAHASHI,  

[Date]2015/2/23
[Paper #]VLD2014-156
Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming

Masato ITO,  Qing DONG,  Shigetoshi NAKATAKE,  

[Date]2015/2/23
[Paper #]VLD2014-157
Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing

Hayato MASHIKO,  Yukihide KOHIRA,  

[Date]2015/2/23
[Paper #]VLD2014-158
Studies on Representation of Stacked Rectangular Dissections for 3D-LSI Floorplan

Kazufumi KOGAI,  Kunihiro FUJIYOSHI,  

[Date]2015/2/23
[Paper #]VLD2014-159
A High Stability and Low Leakage Current Six-Transistor CMOS SRAM Employing a Single Low Supply Voltage

Nobuaki Kobayashi,  Ryusuke Ito,  Koji Motojima,  Tadayoshi Enomoto,  

[Date]2015/2/23
[Paper #]VLD2014-160
A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture

Song BIAN,  Michihiro SHINTANI,  Zheng WANG,  Masayuki HIROMOTO,  Anupam CHATTOPADHYAY,  Takashi SATO,  

[Date]2015/2/23
[Paper #]VLD2014-161
A low-power soft error tolerant latch scheme

Saki TAJIMA,  Youhua SHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  

[Date]2015/2/23
[Paper #]VLD2014-162
Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI

Michitarou YABUUCHI,  Kazutoshi KOBAYASHI,  

[Date]2015/2/23
[Paper #]VLD2014-163
ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths

Junghoon OH,  Mineo KANEKO,  

[Date]2015/2/23
[Paper #]VLD2014-164
Generation of Asynchronous Circuits from a High-level Synthesis Tool

Taichi KOMINE,  Hiroshi SAITO,  

[Date]2015/2/23
[Paper #]VLD2014-165
A Design of FIR filters using High Level Synthesis : A automated design of FIR filters

Ryo YAMAMOTO,  Naoya OKADA,  Noriyuki MINEGISHI,  

[Date]2015/2/23
[Paper #]VLD2014-166
A Virtual/Real Combined Verification Method for FPGAs

Yoshimasa ISHINO,  

[Date]2015/2/23
[Paper #]VLD2014-167
Research in Industry and University for VLSI Design

Satoshi GOTO,  

[Date]2015/2/23
[Paper #]VLD2014-168
Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator

Shoichi IIZUKA,  Yuma HIGUCHI,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2015/2/23
[Paper #]VLD2014-169
A Performance Enhanced Dual-switch Network-on-Chip Architecture

Lian Zeng,  Takahiro Watanabe,  

[Date]2015/2/23
[Paper #]VLD2014-170
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