IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2013/09/30)

Presentation

表紙

[Date]2013/9/30
[Paper #]

A Memory Based Filed Programmable Device for Energy saving MCUs

Tetsuya Matsumura, Yoshifumi KAWAMURA, Naoya OKADA, Kazutami ARIMOTO, Makino HIROSHI, Yoshio MATSUDA,

[Date]2013/9/30
[Paper #]VLD2013-46,ICD2013-70,IE2013-46

Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits

Masashi IMAI, Tomohiro YONEDA,

[Date]2013/9/30
[Paper #]VLD2013-47,ICD2013-71,IE2013-47

Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit

Atsushi ITO, Makoto IKEDA,

[Date]2013/9/30
[Paper #]VLD2013-48,ICD2013-72,IE2013-48

Technology Trends and Researches in Video Codec LSI

Satoshi GOTOSHI,

[Date]2013/9/30
[Paper #]VLD2013-49,ICD2013-73,IE2013-49

Standardization of HEVC/H.265 and a Real-time Encoder

Hiroharu SAKATE, Nobuaki MOTOYAMA,

[Date]2013/9/30
[Paper #]VLD2013-50,ICD2013-74,IE2013-50

High Speed Block Motion Estimation (BME) Employing "Picture Frame shaped Search Window (PFSW)" for 8K Ultra High Definition Television (UHDTV)

Kentaro Seki, Tadayoshi Enomoto,

[Date]2013/9/30
[Paper #]VLD2013-51,ICD2013-75,IE2013-51

A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

Guangji HE, Yuki MIYAMOTO, IZUMI Shintaro /, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO,

[Date]2013/9/30
[Paper #]VLD2013-52,ICD2013-76,IE2013-52

Set Operating Processor (SOP) : Application for Image recognition

Katsumi INOUE, Duc-Hung LE, Masahiro SOWA, Cong-Kha PHAM,

[Date]2013/9/30
[Paper #]VLD2013-53,ICD2013-77,IE2013-53

A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations

Yuta HAGIO, Masao YANAGISAWA, Nozomu TOGAWA,

[Date]2013/9/30
[Paper #]VLD2013-54,ICD2013-78,IE2013-54

Scan-based Attack on the LED Block Cipher Using Scan Signatures

Mika FUJISHIRO, Masao YANAGISAWA, Nozomu TOGAWA,

[Date]2013/9/30
[Paper #]VLD2013-55,ICD2013-79,IE2013-55

A Bi-Linear Interpolation Unit Using Selector Logics

Masashi SHIO, Masao YANAGISAWA, Nozomu TOGAWA,

[Date]2013/9/30
[Paper #]VLD2013-56,ICD2013-80,IE2013-56

New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic

Xu BAI, Michitaka KAMEYAMA,

[Date]2013/9/30
[Paper #]VLD2013-57,ICD2013-81,IE2013-57

A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage

Nobuaki Kobayashi, Tadayoshi Enomoto,

[Date]2013/9/30
[Paper #]VLD2013-58,ICD2013-82,IE2013-58

A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements

Yu ZHANG, Mingyu LI, Qing DONG, Shigetoshi NAKATAKE, Bo YANG,

[Date]2013/9/30
[Paper #]VLD2013-59,ICD2013-83,IE2013-59

A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects

Gong CHEN, Mingyu LI, Qing DONG, Shigetoshi NAKATAKE, Bo YANG,

[Date]2013/9/30
[Paper #]VLD2013-60,ICD2013-84,IE2013-60

複写される方へ

[Date]2013/9/30
[Paper #]

Notice for Photocopying

[Date]2013/9/30
[Paper #]

奥付

[Date]2013/9/30
[Paper #]