Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2013/02/25)

Presentation
表紙

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[Date]2013/2/25
[Paper #]
目次

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[Date]2013/2/25
[Paper #]
正誤表

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[Date]2013/2/25
[Paper #]
A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application

Junpei KAMEI,  Shingo MATSUKI,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2013/2/25
[Paper #]VLD2012-136
Acceleration of current-threshold determination toward on-line IDDQ testing through parameter estimation

Michihiro SHINTANI,  Takashi SATO,  

[Date]2013/2/25
[Paper #]VLD2012-137
Self-Compensation of Manufacturing Variability using On-Chip Sensors

Yuma HIGUCHI,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2013/2/25
[Paper #]VLD2012-138
APR-based Legalization Method

Shota HIRAE,  Maho ISHIKAWA,  Yasuhiro TAKASHIMA,  

[Date]2013/2/25
[Paper #]VLD2012-139
TSV-aware Analytical Placement

Koji MORITA,  Yasuhiro TAKASHIMA,  

[Date]2013/2/25
[Paper #]VLD2012-140
Analytical Placement for Rectilinear Blocks

Tomoaki GOTANDA,  Yasuhiro TAKASHIMA,  

[Date]2013/2/25
[Paper #]VLD2012-141
The minimum perturbation placement realization for convex blocks

Hiroki MATSUGANO,  Shouta HIRAE,  Yasuhiro TAKASHIMA,  

[Date]2013/2/25
[Paper #]VLD2012-142
An Automatic Nested Loop Pipelining method from C level behavior description

Masahiro NAMBU,  Takashi KAMBE,  

[Date]2013/2/25
[Paper #]VLD2012-143
An Acceleration method and its evaluation for Coarse Grained Reconfigurable Circuit Synthesis

Nobuyuki ARAKi,  Takashi KAMBE,  

[Date]2013/2/25
[Paper #]VLD2012-144
High Level Resynthesis Approach of Reusable RTL Property

Masato TATSUOKA,  Mineo KANEKO,  

[Date]2013/2/25
[Paper #]VLD2012-145
A Multi-Task Scheduling and Allocation for Highly Reliable Network-on-Chip

Hiroshi SAITO,  Tomohiro YONEDA,  Yuichi NAKAMURA,  

[Date]2013/2/25
[Paper #]VLD2012-146
Cyber-Physical Systems and LSI Design Technologies

Shinpei KATO,  Masato EDAHIRO,  

[Date]2013/2/25
[Paper #]VLD2012-147
An optimal Design Method for Input Signals of Small SoG-LCDs and Its Evaluation

Taichi SUIZU,  Shuji TSUKIYAMA,  

[Date]2013/2/25
[Paper #]VLD2012-148
A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing

Kyosuke SHINODA,  Atsushi TAKAHASHI,  

[Date]2013/2/25
[Paper #]VLD2012-149
A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors

Yasuhiro SHINTANI,  Masato INAGI,  Shinobu NAGAYAMA,  Shin'ichi WAKABAYASHI,  

[Date]2013/2/25
[Paper #]VLD2012-150
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality

Keitarou OKA,  Hiroshi SASAKI,  Koji INOUE,  

[Date]2013/2/25
[Paper #]VLD2012-151
An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation

Michihiro SHINTANI,  Takashi SATO,  

[Date]2013/2/25
[Paper #]VLD2012-152
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