Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2012/02/28)

Presentation
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[Date]2012/2/28
[Paper #]
目次

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[Date]2012/2/28
[Paper #]
Global Process Parameter Estimation Using IDDQ Current Signature

Michihiro SHINTANI,  Takashi SATO,  

[Date]2012/2/28
[Paper #]VLD2011-120
Performance evaluation and Improvement of Via Programmable Logic VPEX

Taku Otani,  Ryohei Hori,  Tatsuya Kitamori,  Taisuke Ueoka,  Masaya Yoshikawa,  Takeshi Fujino,  

[Date]2012/2/28
[Paper #]VLD2011-121
LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems: COOL Chip

Hiroyuki UCHIDA,  Michiya HAGIMOTO,  Tomoyuki MORIMOTO,  Nobuyuki HIKICHI,  Yukoh MATSUMOTO,  Fumito IMURA,  Naoya WATANABE,  Katsuya KIKUCHI,  Motohiro SUZUKI,  Hiroshi NAKAGAWA,  Masahiro AOYAGI,  

[Date]2012/2/28
[Paper #]VLD2011-122
An Evaluation of the Speedup Method for Power Grid Circuit Simulation by GPGPU

Hayato SHIONO,  Lin LEI,  Makoto YOKOTA,  Masahiro FUKUI,  

[Date]2012/2/28
[Paper #]VLD2011-123
10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control

Sadayuki YASUDA,  Takahiro HATANO,  Hiroki SUTO,  Masami URANO,  Mamoru NAKANISHI,  Tsugumichi SHIBATA,  

[Date]2012/2/28
[Paper #]VLD2011-124
Implementation of Tamper-Resistant Cryptographic DES Circuit using Dual-Rail RSL Memory

Megumi SHIBATANI,  Katsuhiko IWAI,  Mitsuru SHIOZAKI,  Shunsuke ASAGAWA,  Takeshi FUJINO,  

[Date]2012/2/28
[Paper #]VLD2011-125
A Loop Pipeling Method for Irregular Nested Loops

Takashi TAKENAKA,  Kazutoshi WAKABAYASHI,  Yuka NAKAGOSHI,  

[Date]2012/2/28
[Paper #]VLD2011-126
Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability

Yosuke HARUTA,  Mineo KANEKO,  

[Date]2012/2/28
[Paper #]VLD2011-127
High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions

Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2012/2/28
[Paper #]VLD2011-128
CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis

Shinji OHNO,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2012/2/28
[Paper #]VLD2011-129
Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools

Takehiro MIKAMI,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2012/2/28
[Paper #]VLD2011-130
A Length Matching Routing Algorithm on Single Layer using Longer Path Algorithm for Single Net

Syouhei FURUYAMA,  Yukihide KOHIRA,  

[Date]2012/2/28
[Paper #]VLD2011-131
A Power Grid Optimization Algorithm Considering by NBTI

Yoriaki NAGATA,  Masahiro FUKUI,  Shuji TSUKIYAMA,  

[Date]2012/2/28
[Paper #]VLD2011-132
Design automation of highly reliable VLSI by redundancy FF replacement method

Ken Yano,  Takahito Yoshiki,  Takanori Hayashida,  Toshinori Sato,  

[Date]2012/2/28
[Paper #]VLD2011-133
An Efficient Method to Analyze Logic Masking Effects of Soft Errors in Sequential Circuits

Taiga TAKATA,  Yusuke MATSUNAGA,  

[Date]2012/2/28
[Paper #]VLD2011-134
Equivalence checking method of timed logic formulae for verification of single-flux-quantum circuit

Takahiro KAWAGUCHI,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2012/2/28
[Paper #]VLD2011-135
Implementation of Look-ahead Assertion for Pattern-independent Regular Expression Matching Engine

Yoichi WAKABA,  Shinobu NAGAYAMA,  Masato INAGI,  Shin'ichi WAKABAYASHI,  

[Date]2012/2/28
[Paper #]VLD2011-136
An Implementation of Real-time Image Recognition Hardware for Many Cameras

Eiichi HOSOYA,  Takashi AOKI,  Takuya OTSUKA,  Yusuke SEKIHARA,  Akira ONOZAWA,  

[Date]2012/2/28
[Paper #]VLD2011-137
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