Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2011/09/19)

Presentation
表紙

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[Date]2011/9/19
[Paper #]
目次

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[Date]2011/9/19
[Paper #]
A transistor-level symmetrical layout generation method for analog device

Bo Yang,  Qing Dong,  Jing Li,  Shigetoshi Nakatake,  

[Date]2011/9/19
[Paper #]VLD2011-40
CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects

Yu ZHANG,  Gong CHEN,  Qing DONG,  Jing LI,  Bo YANG,  Shigetoshi NAKATAKE,  

[Date]2011/9/19
[Paper #]VLD2011-41
MSA : Mixed Stochastic Algorithm for Placement with Larger Solution Space

Yiqiang SHENG,  Atsushi TAKAHASHI,  Shuichi UENO,  

[Date]2011/9/19
[Paper #]VLD2011-42
Analytical Placement for Closed-Symmetrical Placement

Yasuhiro TAKASHIMA,  Yusuke OYA,  

[Date]2011/9/19
[Paper #]VLD2011-43
On set pair routing problem

Atsushi TAKAHASHI,  

[Date]2011/9/19
[Paper #]VLD2011-44
Bondage : A Legal Interconnect to Define a Reasonable Pin Placement

Yoji KAJITANI,  

[Date]2011/9/19
[Paper #]VLD2011-45
A Reconfigurable Layout Method and Evaluation for Network on Chip

Yuichi Nakamura,  

[Date]2011/9/19
[Paper #]VLD2011-46
Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD^

Masato INAGI,  Mosatoshi NAKAMURA,  Tetsuo HIRONAKA,  Takashi ISHIGURO,  

[Date]2011/9/19
[Paper #]VLD2011-47
A Design Method of Network-on-Chip Architecture for FPGA

Hideki KATABAMI,  Hiroshi SAITO,  

[Date]2011/9/19
[Paper #]VLD2011-48
A statistical evaluation of approximate methods for soft error tolerance analysis of combinational circuits

Hidenori AYABE,  Masayoshi YOSHIMURA,  Yusuke MATSUNAGA,  

[Date]2011/9/19
[Paper #]VLD2011-49
Acceleration of Smith-Waterman Algorithm Using Pipelined Array Processor

Asuka TANAKA,  Shizuka Ishikawa,  Toshiaki MIYAZAKI,  

[Date]2011/9/19
[Paper #]VLD2011-50
Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis

Keisuke INOUE,  Mineo KANEKO,  

[Date]2011/9/19
[Paper #]VLD2011-51
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[Date]2011/9/19
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[Date]2011/9/19
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[Date]2011/9/19
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[Date]2011/9/19
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