Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2010/05/12)

Presentation
表紙

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[Date]2010/5/12
[Paper #]
目次

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[Date]2010/5/12
[Paper #]
High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation

Akira OHCHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2010/5/12
[Paper #]VLD2010-1
Highly Accurate Approximate Methods for Soft Error Tolerance Estimation for Sequential Circuits

Naoki SHIROBAYASHI,  Yusuke AKAMINE,  Masayoshi YOSHIMURA,  Yusuke MATSUNAGA,  

[Date]2010/5/12
[Paper #]VLD2010-2
An Approximate Method for Steady State Probability Calculation based on FSM Splitting

So HASEGAWA,  Yusuke AKAMINE,  Masayoshi YOSHIMURA,  Yusuke MATSUNAGA,  

[Date]2010/5/12
[Paper #]VLD2010-3
Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architectures

Hiroshi YUASA,  Takashi IMAGAWA,  Masayuki HIROMOTO,  Hiroyuki OCHI,  Takashi SATO,  

[Date]2010/5/12
[Paper #]VLD2010-4
3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

Makoto Saen,  Kenichi Osada,  Yasuyuki Okuma,  Yasuhisa Shimazaki,  Itaru Nonomura,  Kiichi Niitsu,  Yasufumi Sugimori,  Yoshinori Kohama,  Kazutaka Kasuga,  Tadahiro Kuroda,  

[Date]2010/5/12
[Paper #]VLD2010-5
Implementation of error correction method on small area and low power consumption processor for the capsular detrusor pressure measurement system

Hiroki OHSAWA,  Tomohiro KONDO,  Hirofumi IWATO,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2010/5/12
[Paper #]VLD2010-6
A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control

Masafumi ONOUCHI,  Yusuke KANNO,  Makoto SAEN,  Shigenobu KOMATSU,  Yoshihiko YASU,  Koichiro ISHIBASHI,  

[Date]2010/5/12
[Paper #]VLD2010-7
Temperature-dependent model for break-even time in fine-grain power gating and adaptive control based on the temperature dependence

Kimiyoshi USAMI,  Tatsunori HASHIDA,  

[Date]2010/5/12
[Paper #]VLD2010-8
An Efficient Congested Area Specification and Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Rouitng

Kyosuke SHINODA,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2010/5/12
[Paper #]VLD2010-9
Variation Modeling of Current Sources by D/A Converter Analysis

Bo LIU,  Qing DONG,  Bo YANG,  Shigetoshi NAKATAKE,  

[Date]2010/5/12
[Paper #]VLD2010-10
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[Date]2010/5/12
[Paper #]
奥付

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[Date]2010/5/12
[Paper #]
電子情報通信学会学生員になろう

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[Date]2010/5/12
[Paper #]