Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2010/03/03)

Presentation
表紙

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[Date]2010/3/3
[Paper #]
目次

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[Date]2010/3/3
[Paper #]
An Automatic Layout System for Timing Pulse Generator of Small LCD Driver Circuits

Shohei ASAKAWA,  Yuichi SAKAKIBARA,  Shuji TSUKIYAMA,  Isao SHIRAKAWA,  Shuji NISHI,  Tadashi TAKEDA,  Tomoyuki NAGAI,  Yasushi KUBOTA,  

[Date]2010/3/3
[Paper #]VLD2009-99
Analog Macro Layout Generation Based on Regular Bulk Structure

Bo YANG,  Qing DONG,  Jing LI,  Shigetoshi NAKATAKE,  

[Date]2010/3/3
[Paper #]VLD2009-100
Circuit Structure of Level Shifter for Sub-threshold Operation

Tomohiro ISHIZAKI,  Satoshi KOYAMA,  Kimiyoshi USAMI,  

[Date]2010/3/3
[Paper #]VLD2009-101
A Delay Variation Modeling Algorithm with Considering Supply Voltage and Local Temperature

Hideki YANAGAWA,  Haruo MIKI,  Masahiro FUKUI,  Shuji TSUKIYAMA,  

[Date]2010/3/3
[Paper #]VLD2009-102
Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transistors

Chikara HAMANAKA,  Jun FURUTA,  Hiroaki MAKNO,  Kazutoshi KOBAYASHI,  Hidetoshi ONODERA,  

[Date]2010/3/3
[Paper #]VLD2009-103
Variation-Tolerant Decomposition of MOS Transistor

Bo LIU,  Atsushi OCHI,  Shigetoshi NAKATAKE,  

[Date]2010/3/3
[Paper #]VLD2009-104
An efficient technique to search failure-areas for yield estimation via partial hypersphere

Takanori DATE,  Shiho HAGIWARA,  Kazuya MASU,  Takashi SATO,  

[Date]2010/3/3
[Paper #]VLD2009-105
Changing Organization through Continuous Data Collection with Business Microscope

Koji ARA,  Nobuo SATO,  Kazuo YANO,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2010/3/3
[Paper #]VLD2009-106
Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block

Shota Yamada,  Yuuichi Kokushou,  Tomohiro Nishimoto,  Naoyuki Yoshida,  Ryouhei Hori,  Naoki Matsumoto,  Tatsuya Kitamori,  Masaya Yoshikawa,  Takeshi Fujino,  

[Date]2010/3/3
[Paper #]VLD2009-107
Examination of the best basic logic gate architecture for Via programmable logic device

Ryouhei Hori,  Yuichi Kokusho,  Tomohiro Nishimoto,  Shota Yamada,  Naoyuki Yoshida,  Naoki Matsumoto,  Takeshi Fujino,  Masaya Yosikawa,  

[Date]2010/3/3
[Paper #]VLD2009-108
Wiring delay of Logic Element used in Via programmable logic device VPEX

Tomohiro NISHIMOTO,  Tatuya KITAMORI,  Yuichi KOKUSYOU,  Shouta YAMADA,  Masaya YOSHIKAWA,  Takeshi FUJINO,  

[Date]2010/3/3
[Paper #]VLD2009-109
High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties

Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2010/3/3
[Paper #]VLD2009-110
On an Accuracy Improvement of a Statistical Timing Analysis Using Gaussian Mixture Models

Atsutaka OBATA,  Shuji TSUKIYAMA,  Masahiro FUKUI,  

[Date]2010/3/3
[Paper #]VLD2009-111
Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests

Takanobu SHIKI,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2010/3/3
[Paper #]VLD2009-112
Implementation Scheme for Power Gating and its Influence to Energy Reduction

Yuya OHTA,  Satoshi KOYAMA,  Tatsunori HASHIDA,  Tetsuya MUTO,  Tatsuya YAMAMOTO,  Kimiyoshi USAMI,  

[Date]2010/3/3
[Paper #]VLD2009-113
A Break Even Time Prediction of Run-Time Power Gating Circuits by an On-chip Leakage Monitor using an MTCMOS circuit

Satoshi KOYAMA,  Tatsunori HASHIDA,  Kimiyoshi USAMI,  Daisuke Ikebuchi,  Hideharu AMANO,  

[Date]2010/3/3
[Paper #]VLD2009-114
Fast Estimation Method of Peak Power considering Input Vector and Inner State of a Circuit

Nobuyoshi TAKAHASHI,  Yoichi TOMIOKA,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2010/3/3
[Paper #]VLD2009-115
Analytical Evaluation of Average Switching Energy of Adders

Shinji OHNO,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2010/3/3
[Paper #]VLD2009-116
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