Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2009/09/17)

Presentation
表紙

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[Date]2009/9/17
[Paper #]
目次

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[Date]2009/9/17
[Paper #]
Fast Global Floorplanning Method Based on Stable-LSE

Yasuhiro TAKASHIMA,  Masatomo KUWANO,  

[Date]2009/9/17
[Paper #]VLD2009-29
A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages

Masaki KINOSHITA,  Yoichi TOMIOKA,  Atsushi TAKAHASHI,  

[Date]2009/9/17
[Paper #]VLD2009-30
A Wall Generation for Trunk Routing of Multiple Nets on Single Layer

Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2009/9/17
[Paper #]VLD2009-31
Complete ILP-Formulation of High-Level Synthesis

Keisuke INOUE,  Mineo KANEKO,  

[Date]2009/9/17
[Paper #]VLD2009-32
A System LSI Design and Verification Environment Using JACKAL Language

Takafumi KOHARA,  Ryuichi NAKAWAKI,  Yasuhiro NAGATA,  Takashi KAMBE,  

[Date]2009/9/17
[Paper #]VLD2009-33
On accelleration of SER analysis for sequential circuits using implicit enumeration

Yusuke MATSUNAGA,  Yusuke AKAMINE,  

[Date]2009/9/17
[Paper #]VLD2009-34
マルチプロセッサシステムオンチップのためのトレース駆動型ワークロードシミュレーション手法(物理設計及び一般)

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[Date]2009/9/17
[Paper #]VLD2009-35
An Approach for Algorithm Tuning Power Grid Simulation by GPGPU

Makoto YOKOTA,  Yuuya ISODA,  Hisako SUGANO,  Ittetsu TANIGUCHI,  Masahiro FUKUI,  

[Date]2009/9/17
[Paper #]VLD2009-36
Triage Device Slightly Injured Person in Disaster Medical Assistant Network

Keishi SAKANUSHI,  Akihito HIROMORI,  Taichiro IMAMURA,  Junya OKAMOTO,  Takuji HIEDA,  Yoshinori TAKEUCHI,  Masaharu IMAI,  Junji KITAMICHI,  Teruo HIGASHINO,  

[Date]2009/9/17
[Paper #]VLD2009-37
High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE802.11n Standard

Akiyuki NAGASHIMA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2009/9/17
[Paper #]VLD2009-38
DFG Mapping for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm

Ryo TAMURA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  Makoto SATOH,  

[Date]2009/9/17
[Paper #]VLD2009-39
A remote optically reconfigurable gate array using fibers

Yumiko UENO,  Minoru WATANABE,  

[Date]2009/9/17
[Paper #]VLD2009-40
A configuration speed acceleration method using negative logic implementation

Retsu MORIWAKI,  Minoru WATANABE,  

[Date]2009/9/17
[Paper #]VLD2009-41
Defect tolerance of a MEMS dynamic optically reconfigurable gate array

Daisaku SETO,  Minoru WATANABE,  

[Date]2009/9/17
[Paper #]VLD2009-42
複写される方へ

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[Date]2009/9/17
[Paper #]
Notice for Photocopying

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[Date]2009/9/17
[Paper #]
奥付

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[Date]2009/9/17
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