Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2009/03/04)

Presentation
表紙

,  

[Date]2009/3/4
[Paper #]
目次

,  

[Date]2009/3/4
[Paper #]
Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution

Tetsuya YAMAMOTO,  Nagisa ISHIURA,  Takahiro KUMURA,  Masao IKEKAWA,  Masaharu IMAI,  

[Date]2009/3/4
[Paper #]VLD2008-126
Random Testing for Arithmetic Optimization of C compilers

Hironobu AWAZU,  Nagisa ISHIURA,  

[Date]2009/3/4
[Paper #]VLD2008-127
Execution Trace Mining for Intratask DVFS in Embedded Systems

Tomohiro TATEMATSU,  Tetsuo YOKOYAMA,  Takehiko KIKUCHI,  Hiroyuki TOMIYAMA,  Hiroaki TAKADA,  

[Date]2009/3/4
[Paper #]VLD2008-128
Model-Based Development for automotive control system : Modeling Technique of microcontroller

Yasuo SUGURE,  Shigeru OHO,  

[Date]2009/3/4
[Paper #]VLD2008-129
Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis

Keisuke INOUE,  Mineo KANEKO,  Tsuyoshi IWAGAKI,  

[Date]2009/3/4
[Paper #]VLD2008-130
Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints

Sho KODAMA,  Yusuke MATSUNAGA,  

[Date]2009/3/4
[Paper #]VLD2008-131
Fault Tolerant Datapath Synthesis Starting with Triple Algorithmic Redundancy

Yutaka TSUBOISHI,  Mineo KANEKO,  

[Date]2009/3/4
[Paper #]VLD2008-132
On the Minimization of Input Variables for Incompletely Specified Index Generation Functions

Takaaki NAKAMURA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2009/3/4
[Paper #]VLD2008-133
A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool

Hiroyoshi HASHIMOTO,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2009/3/4
[Paper #]VLD2008-134
A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits

Shuhei TANI,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2009/3/4
[Paper #]VLD2008-135
A Maximization Method of Parallel Wire Lengths in Routing Area with Obstacles

Suguru SUEHIRO,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2009/3/4
[Paper #]VLD2008-136
Fast Optimization on Minimum Perturbation Placement Realization

Yuki KOUNO,  Yasuhiro TAKASHIMA,  Atsushi TAKAHASHI,  

[Date]2009/3/4
[Paper #]VLD2008-137
Delay Estimation of Sub-path under Path-delay Test

Takanobu SHIKI,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2009/3/4
[Paper #]VLD2008-138
Chip evaluation and implementation of DES encryption using via-programmable-device VPEX

Masahide Kawarasaki,  Tomohiro Nishimoto,  Yuuichi Kokushou,  Kazuma Kitamura,  Syouta Yamada,  Masaya Yoshikawa,  Takeshi Fujino,  

[Date]2009/3/4
[Paper #]VLD2008-139
The implementation of DES cryptographic circuit and the evaluation of DPA attack resistance using Domino-RSL technique

Kenji KOJIMA,  Kazuki OKUYAMA,  Yuki MAKINO,  Takeshi FUJINO,  

[Date]2009/3/4
[Paper #]VLD2008-140
Differential Power Analysis of bit-value against cipher implementation on FPGA

Kazuki OKUYAMA,  Kenji KOJIMA,  Yuki MAKINO,  Takeshi FUJINO,  

[Date]2009/3/4
[Paper #]VLD2008-141
A Formal Verification Method for On-Chip Programmable Interconnect

Takaaki TAGAWA,  Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2009/3/4
[Paper #]VLD2008-142
High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit

Naoki MIURA,  Satoshi SHIGEMATSU,  Takahiro HATANO,  Yusuke AKAMINE,  Mamoru NAKANISHI,  Masami URANO,  

[Date]2009/3/4
[Paper #]VLD2008-143
123>> 1-20hit(48hit)