Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2009/01/22)

Presentation
表紙

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[Date]2009/1/22
[Paper #]
目次

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[Date]2009/1/22
[Paper #]
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction

Toru SANO,  Hideharu AMANO,  

[Date]2009/1/22
[Paper #]VLD2008-91,CPSY2008-53,RECONF2008-55
Evaluation of a Multicore Reconfigurable Architecture

TUAN Vu MANH,  Hiroki MATSUTANI,  Naohiro KATSURA,  Hideharu AMANO,  

[Date]2009/1/22
[Paper #]VLD2008-92,CPSY2008-54,RECONF2008-56
Leakage Power Reduction of a Dynamically Reconfigurable Processor using the dual Vth technique

Keiichiro HIRAI,  Toru SANO,  Masaru KATO,  Hideharu AMANO,  

[Date]2009/1/22
[Paper #]VLD2008-93,CPSY2008-55,RECONF2008-57
Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array

Kazuki SATO,  Baatarsuren BARS,  Masatoshi SEKINE,  

[Date]2009/1/22
[Paper #]VLD2008-94,CPSY2008-56,RECONF2008-58
FPGA Implementation of Metastability-based True Random Number Generator

Hisashi HATA,  Shuichi ICHIKAWA,  

[Date]2009/1/22
[Paper #]VLD2008-95,CPSY2008-57,RECONF2008-59
A Proposal of Message Driven IP Core Interface

Ryuta SASAKI,  Tsugio NAKAMURA,  Narito FUYUTSUME,  Hiroshi KASAHARA,  Teruo TANAKA,  

[Date]2009/1/22
[Paper #]VLD2008-96,CPSY2008-58,RECONF2008-60
A programmable 9-contexts optically reconfigurable gate arrays and its writer

Shinya KUBOTA,  Minoru WATANABE,  

[Date]2009/1/22
[Paper #]VLD2008-97,CPSY2008-59,RECONF2008-61
Perfect demonstration of a four-context Optically Reconfigurable Gate Array

Takayuk MABUCHI,  Minoru WATANABE,  

[Date]2009/1/22
[Paper #]VLD2008-98,CPSY2008-60,RECONF2008-62
Comparison evaluation of an inversion/non-inversion dynamic optically reconfiguration architecture

Shinichi KATO,  Minoru WATANABE,  

[Date]2009/1/22
[Paper #]VLD2008-99,CPSY2008-61,RECONF2008-63
Circuit Partition Method with Time-mutiplexed I/O

Tatsuki ISOMURA,  Masato INAGI,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2009/1/22
[Paper #]VLD2008-100,CPSY2008-62,RECONF2008-64
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs

Taiga TAKATA,  Yusuke MATSUNAGA,  

[Date]2009/1/22
[Paper #]VLD2008-101,CPSY2008-63,RECONF2008-65
A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length

Shohei HASHIMOTO,  Yuta TOTSUKA,  Masamichi MAKINO,  Hikaru YASUDA,  Tsugio NAKAMURA,  Narito FUYUTSUME,  Hiroshi KASAHARA,  

[Date]2009/1/22
[Paper #]VLD2008-102,CPSY2008-64,RECONF2008-66
Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core

Yuta MIZOKAMI,  Mitsutaka NAKANO,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2009/1/22
[Paper #]VLD2008-103,CPSY2008-65,RECONF2008-67
テスト用Linuxクラスタシステムの試作(コンピュータシステム技術,FPGA応用及び一般)

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[Date]2009/1/22
[Paper #]VLD2008-104,CPSY2008-66,RECONF2008-68
Extension of High Level Synthesis System CCAP for AMP Multi-Core System Design

Yoshiyuki ISHIMORI,  Nagisa ISHIURA,  Hiroyuki TOMIYAMA,  Hiroyuki KANBARA,  

[Date]2009/1/22
[Paper #]VLD2008-105,CPSY2008-67,RECONF2008-69
A Tunable LSI Based on Timing Skew and Stall Adjustments

Yayumi UEHARA,  Mineo KANEKO,  

[Date]2009/1/22
[Paper #]VLD2008-106,CPSY2008-68,RECONF2008-70
Fast Module Placement in Floorplan-aware High-level Synthesis

Wataru SATO,  Akira OHCHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2009/1/22
[Paper #]VLD2008-107,CPSY2008-69,RECONF2008-71
A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors

Takayuki WATANABE,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2009/1/22
[Paper #]VLD2008-108,CPSY2008-70,RECONF2008-72
12>> 1-20hit(40hit)