Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2008/11/10)

Presentation
表紙

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[Date]2008/11/10
[Paper #]
目次

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[Date]2008/11/10
[Paper #]
On Improving Transition Fault Coverage of Stuck-at Fault Tests Using Don't Care Identification Technique

Kazumitsu HAMASAKI,  Toshinori HOSOKAWA,  

[Date]2008/11/10
[Paper #]VLD2008-60,DC2008-28
An Integer Programming Formulation for Generating High Quality Transition Tests

Tsuyoshi IWAGAKI,  Mineo KANEKO,  

[Date]2008/11/10
[Paper #]VLD2008-61,DC2008-29
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Atsushi TAKASHIMA,  Yuta YAMATO,  Hiroshi FURUKAWA,  Kohei MIYASE,  Xiaoqing WEN,  Seiji KAJIHARA,  

[Date]2008/11/10
[Paper #]VLD2008-62,DC2008-30
Analysis of Open Faults using TEG Chip

Toshiyuki TSUTSUMI,  Yasuyuki KARIYA,  Koji YAMAZAKI,  Masaki HASHIZUME,  Hiroyuki YOTSUYANAGI,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Yuzo TAKAMATSU,  

[Date]2008/11/10
[Paper #]VLD2008-63,DC2008-31
Area Efficient Multipliers Utilizing the Sum of Operands

Hirotaka KAWASHIMA,  Naofumi TAKAGI,  

[Date]2008/11/10
[Paper #]VLD2008-64,DC2008-32
Hardware Algorithm for Division in GF (2^m) Based on the Extended Euclid's Algorithm Accelerated with Parallelization of Modular Reductions

Katsuki KOBAYASHI,  Naofumi TAKAGI,  

[Date]2008/11/10
[Paper #]VLD2008-65,DC2008-33
Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit

Akiyuki NAGASHIMA,  Yuta IMAI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-66,DC2008-34
A Parallel Hardware Engine for Generating Deformed Maps

Akira ARAHATA,  Ryuta NARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-67,DC2008-35
Scan-based Attack for an AES-LSI included with other IPs

Ryuta NARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-68,DC2008-36
Dynamically Variable Secure Scan Architecture against Scan-based Side Channel Attack on Cryptography LSIs

Hiroshi ATOBE,  Ryuta NARA,  Youhua SHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-69,DC2008-37
A Power Masking Method of AES Circuit by Using Cross Bar Switch to Switch S-Box Circuit

Nobuyuki KAWAHATA,  Ryuta NARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-70,DC2008-38
On Handling Cell Placement with Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design

Shimpei ASANO,  Kunihiro FUJIYOSHI,  

[Date]2008/11/10
[Paper #]VLD2008-71,DC2008-39
CAFE router : A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles

Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2008/11/10
[Paper #]VLD2008-72,DC2008-40
Coarse-Grained Reconfigurable Architecture with Flexible Reliability

Younghun KO,  Dawood ALNAJJAR,  Yukio MITSUYAMA,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2008/11/10
[Paper #]VLD2008-73,DC2008-41
Insertion-Point Selection of Canary FF for Timing Error Prediction

YUJI Kunitake,  TOSHINORI Sato,  Seiichiro YAMAGUCHI,  HIROTO Yasuura,  

[Date]2008/11/10
[Paper #]VLD2008-74,DC2008-42
Evaluating the reliability of Highly Reliable Cell Circuits

Keiichi HOTTA,  Takashi NAKADA,  Masaki NAKANISHI,  Shigeru YAMASHITA,  Yasuhiko NAKASHIMA,  

[Date]2008/11/10
[Paper #]VLD2008-75,DC2008-43
A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems

Nobuaki TOJO,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-76,DC2008-44
Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay

Tetsuya NAGASE,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2008/11/10
[Paper #]VLD2008-77,DC2008-45
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