Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2008/05/01)

Presentation
表紙

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[Date]2008/5/1
[Paper #]
目次

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[Date]2008/5/1
[Paper #]
HW/SW Co-verification Method using FPGAs

Yuichi Nakamura,  Kouhei Hosokawa,  

[Date]2008/5/1
[Paper #]VLD2008-1
Checker Circuit Generation for System Verilog Assertions in Prototyping Verification

Mengru WANG,  Shinji KIMURA,  

[Date]2008/5/1
[Paper #]VLD2008-2
Checker Generation of Assertions with Local Variables for Model Checking

Sho TAKEUCHI,  Kiyoharu HAMAGUCHI,  Yosuke KAKIUCHI,  Toshinobu KASHIWABARA,  

[Date]2008/5/1
[Paper #]VLD2008-3
Improvement Technique of Binding for Multiplexer Reduction

Sho KODAMA,  Yusuke MATSUNAGA,  

[Date]2008/5/1
[Paper #]VLD2008-4
Radix-2 Butterfly Circuit Architecture Using Selector Logic

Takeshi NAMURA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  Motonobu TONOMURA,  

[Date]2008/5/1
[Paper #]VLD2008-5
improvement of switching activity aware algorithm for prefix graph synthesis

Taeko MATSUNAGA,  Shinji KIMURA,  Yusuke MATSUNAGA,  

[Date]2008/5/1
[Paper #]VLD2008-6
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[Date]2008/5/1
[Paper #]
奥付

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[Date]2008/5/1
[Paper #]