Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2008/02/29)

Presentation
表紙

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[Date]2008/2/29
[Paper #]
目次

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[Date]2008/2/29
[Paper #]
A delay balancing technique for wave-pipelining

Keiichiro SANO,  Jubee TADA,  Ryusuke EGAWA,  Gensuke GOTO,  

[Date]2008/2/29
[Paper #]VLD2007-156,ICD2007-179
Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit

Kazunori NODA,  Atsuko YOKOYAMA,  Hiroki TAKEDA,  Masa-aki FUKASE,  Tomoaki SATO,  

[Date]2008/2/29
[Paper #]VLD2007-157,ICD2007-180
A Self-timed Processor with Dynamic Voltage Scaling

Taku SOGABE,  Makoto IKEDA,  Kunihiro Asada,  

[Date]2008/2/29
[Paper #]VLD2007-158,ICD2007-181
A high-throughput Architectures for LDPC Coded OFDM Baseband Processor

Shinsuke USHIKI,  Koichi NAKAMURA,  Kazunori SHIMIZU,  Qi WANG,  Yuta Abe,  Satoshi GOTO,  Takeshi IKENAGA,  

[Date]2008/2/29
[Paper #]VLD2007-159,ICD2007-182
Design of High Throughput Multi-rate Irregular LDPC Decoder based on Accelerated Message-Passing Schedule : The Format of Technical Report (Subtitle)

Yuta ABE,  Naoki TAJIMA,  Xing RI,  Kazunori SHIMIZU,  Takeshi IKENAGA,  Satoshi GOTO,  

[Date]2008/2/29
[Paper #]VLD2007-160,ICD2007-183
The Improvement of the Ubiquitous Processor HCgorilla

Hiroki TAKEDA,  Kazunori NODA,  Atsuko YOKOYAMA,  Masa-aki FUKASE,  Tomoaki SATO,  

[Date]2008/2/29
[Paper #]VLD2007-161,ICD2007-184
An adaptive error concealment order in H.264/AVC

Jun Wang,  Takeshi Ikenaga,  Satoshi Goto,  

[Date]2008/2/29
[Paper #]VLD2007-162,ICD2007-185
A Low-cost Speed and Yield Enhancement Method using Enbedded Delay-Detectors on FPGAs

Yohei KUME,  Yuuri SUGIHARA,  Ngo CAM LAI,  Kazutoshi KOBAYASHI,  Hidetoshi ONODERA,  

[Date]2008/2/29
[Paper #]VLD2007-163,ICD2007-186
Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method

Motonori OHTA,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/2/29
[Paper #]VLD2007-164,ICD2007-187
Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX)

Mitsutaka Matsumoto,  Shun Kimura,  Hirofumi Nakano,  Takenobu Iwao,  Yoshihiro Okuno,  Kazutami Arimoto,  Tomonori Izumi,  Takeshi Fujino,  

[Date]2008/2/29
[Paper #]VLD2007-165,ICD2007-188
An Object Oriented System LSI Design Methodology and Its Evaluation

Takafumi KOHARA,  Hiroyuki TERAI,  Seigo MASUOKA,  Akihisa YAMADA,  Takashi KAMBE,  

[Date]2008/2/29
[Paper #]VLD2007-166,ICD2007-189
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor

A. YOSHIDA,  Y. HIGASHI,  W. MIYAZAKI,  T. TANAKA,  T. KAMBE,  

[Date]2008/2/29
[Paper #]VLD2007-167,ICD2007-190
New design technology of independent-gate controlled Double-Gate transistor for systemu LSI

Yu Hiroshima,  Keisuke Okamoto,  Keisuke Koizumi,  Shigeyoshi Watanabe,  

[Date]2008/2/29
[Paper #]VLD2007-168,ICD2007-191
New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI

Yu Hiroshima,  Keisuke Okamoto,  Keisuke Koizumi,  Shigeyoshi Watanabe,  

[Date]2008/2/29
[Paper #]VLD2007-169,ICD2007-192
Design of High Density LSI with Three-Dimensional Transistor FinFET : Effect of Pattern Area Reduction with CMOS Cell Library

Keisuke Okamoto,  Keisuke Koizumi,  Yuu Hirosima,  Shigeyoshi Watanabe,  

[Date]2008/2/29
[Paper #]VLD2007-170,ICD2007-193
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[Date]2008/2/29
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[Date]2008/2/29
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[Date]2008/2/29
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