Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2008/02/27)

Presentation
表紙

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[Date]2008/2/27
[Paper #]
目次

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[Date]2008/2/27
[Paper #]
Automatic synthesis and verification of practical protocol transducer based on product graph exploration

Yuji ISHIKAWA,  Satoshi KOMATSU,  Masahiro FUJITA,  

[Date]2008/2/27
[Paper #]VLD2007-137,ICD2007-160
Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems

Makoto SUGIHARA,  

[Date]2008/2/27
[Paper #]VLD2007-138,ICD2007-161
An Accurate Algorithm for RTL Power Macro-modeling

Masaaki Ohtsuki,  Masato Kawai,  Masahiro Fukui,  

[Date]2008/2/27
[Paper #]VLD2007-139,ICD2007-162
Minimizing Minimum Delay Compensations in Datapath Synthesis

Keisuke INOUE,  Mineo KANEKO,  Tsuyoshi IWAGAKI,  

[Date]2008/2/27
[Paper #]VLD2007-140,ICD2007-163
An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory

Shunitsu KOHARA,  Youhua SHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/2/27
[Paper #]VLD2007-141,ICD2007-164
Analog Floorplan with Soft-Module Configuration

Kentaro MURATA,  Kazuya SASAKI,  Qing DONG,  Jing LI,  Shigetoshi NAKATAKE,  

[Date]2008/2/27
[Paper #]VLD2007-142,ICD2007-165
MOS Analog Module Generation

Akio FUJII,  Takehiko MATSUO,  Toru FUJIMURA,  Bo YANG,  Shigetoshi NAKATAKE,  

[Date]2008/2/27
[Paper #]VLD2007-143,ICD2007-166
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[Date]2008/2/27
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[Date]2008/2/27
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[Date]2008/2/27
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