Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2007/11/14)

Presentation
表紙

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[Date]2007/11/14
[Paper #]
目次

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[Date]2007/11/14
[Paper #]
Social Information Infrastructure and Dependable VLSI

Hiroto YASUURA,  

[Date]2007/11/14
[Paper #]VLD2007-82,DC2007-37,RECONF2007-36
A design method for easily testable multipliers adaptable to various structures of partial product addition

Nobutaka KITO,  Naofumi TAKAGI,  

[Date]2007/11/14
[Paper #]VLD2007-83,DC2007-38
Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning

Thomas Edison YU,  Tomokazu YONEDA,  Krishnendu CHAKRABARTY,  Hideo FUJIWARA,  

[Date]2007/11/14
[Paper #]VLD2007-84,DC2007-39
A Construction Method of Path Delay Fault Detectable Circuits

Takashi WATANABE,  Takeo YOSHIDA,  

[Date]2007/11/14
[Paper #]VLD2007-85,DC2007-40
A Resource Binding Method for Reducing Power Consumption of LSI Data Communications

Hidekazu SETO,  Kazuhito ITO,  

[Date]2007/11/14
[Paper #]VLD2007-86,DC2007-41
Design of Low Energy Array Multipliers by Reducing Signal Transitions in Partial Product Accumulators

Hirotaka KAWASHIMA,  Kazuhiro NAKAMURA,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2007/11/14
[Paper #]VLD2007-87,DC2007-42
A power masking multiplier based on galois field for composite field AES

Nobuyuki KAWAHATA,  Ryuta NARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/11/14
[Paper #]VLD2007-88,DC2007-43
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[Date]2007/11/14
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[Date]2007/11/14
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[Date]2007/11/14
[Paper #]