Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2007/11/13)

Presentation
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[Date]2007/11/13
[Paper #]
目次

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[Date]2007/11/13
[Paper #]
Stuck-at Test Data Compression using Scan FFs with Delay Fault Testability

Kentaroh KATOH,  Kazuteru NAMBA,  Hideo ITO,  

[Date]2007/11/13
[Paper #]VLD2007-70,DC2007-25
A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

Tomoaki FUKUZAWA,  Kohei MIYASE,  Yuta YAMATO,  Hiroshi FURUKAWA,  Xiaoqing WEN,  Seiji KAJIHARA,  

[Date]2007/11/13
[Paper #]VLD2007-71,DC2007-26
An Optimization of Thru Trees for Test Generation Based on Acyclical Testability

Kohsuke MORINAGA,  Nobuya OKA,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2007/11/13
[Paper #]VLD2007-72,DC2007-27
An Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic

Hiroaki SHIMIZU,  Kiyoharu HAMAGUCHI,  Toshinobu KASHIWABARA,  

[Date]2007/11/13
[Paper #]VLD2007-73,DC2007-28
A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications

Seiichiro YAMAGUCHI,  Masanori MUROYAMA,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]2007/11/13
[Paper #]VLD2007-74,DC2007-29
An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors

Yuriko ISHITOBI,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]2007/11/13
[Paper #]VLD2007-75,DC2007-30
A process-variation-aware low-power technique using current control

Kyundong KIM,  Masashi IMAI,  Masaaki KONDO,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2007/11/13
[Paper #]VLD2007-76,DC2007-31
Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit

Yoshinobu TOYODA,  Kenta KIDO,  Yoshiaki SHITABAYASHI,  Takeshi FUJINO,  

[Date]2007/11/13
[Paper #]VLD2007-77,DC2007-32
Comparison of Standard Cell based Non-linear Asynchronous Pipelines

Chammika MANNAKKARA,  Tomohiro YONEDA,  

[Date]2007/11/13
[Paper #]VLD2007-78,DC2007-33
An On-Chip Bus Architecture for Post-Fabrication Timing Calibration

Masaki YAMAGUCHI,  Masanori MUROYAMA,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]2007/11/13
[Paper #]VLD2007-79,DC2007-34
Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing

Masahide Kawarasaki,  Akihiro Nakamura,  Tomoaki Nishimoto,  Yosiaki Shitabayshi,  Takeshi Fujino,  

[Date]2007/11/13
[Paper #]VLD2007-80,DC2007-35
Initial Evaluation of FIR Filter Based on Digit-Serial Computation

Yuhki YAMABE,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2007/11/13
[Paper #]VLD2007-81,DC2007-36
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[Date]2007/11/13
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[Date]2007/11/13
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