Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2007/05/04)

Presentation
表紙

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[Date]2007/5/4
[Paper #]
目次

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[Date]2007/5/4
[Paper #]
Automatic Generation of a Verification Environment for Hardware Units : Application to a Bus Bridge Design

Rafael K. MORIZAWA,  Hiroaki IWASHITA,  Koichiro TAKAYAMA,  

[Date]2007/5/4
[Paper #]VD2007-7
On lower bounds for DAG covering problem and their application to the exact algorithm

Yusuke MATSUNAGA,  

[Date]2007/5/4
[Paper #]VD2007-8
A Clock Deskew Method using PDE with Discrete Delay

Yuko HASHIZUME,  Naoki Otani,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2007/5/4
[Paper #]VD2007-9
An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA

Masayuki HIROMOTO,  Atsuko TAKAHASHI,  Shin'ichi KOUYAMA,  Hiroyuki OCHI,  Yukihiro NAKAMURA,  

[Date]2007/5/4
[Paper #]VD2007-10
Multiplier based on variable GF(2^m) for Elliptic Curve Cryptosystems

Ryuta NARA,  Kazunori SHIMIZU,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/5/4
[Paper #]VD2007-11
On power-conscious approach for prefix graph synthesis

Taeko MATSUNAGA,  Yusuke MATSUNAGA,  

[Date]2007/5/4
[Paper #]VD2007-12
A Flexible Power and Task Modeling for LSI Blocks

Tatsuya KOYAGI,  Masahiro FUKUI,  Resve SALEH,  

[Date]2007/5/4
[Paper #]VD2007-13
A fast maximum delay estimation method for specified yield by statistical static timing analysis

Hiroki FURUYA,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2007/5/4
[Paper #]VD2007-14
An algorithm of power grid optimization for high-level floorplan

Takayuki HAYASHI,  Yoshiyuki KAWAKAMI,  Masahiro FUKUI,  

[Date]2007/5/4
[Paper #]VD2007-15
Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects

Akira TSUCHIYA,  Hidetoshi ONODERA,  

[Date]2007/5/4
[Paper #]VD2007-16
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[Date]2007/5/4
[Paper #]
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[Date]2007/5/4
[Paper #]