Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2007/05/03)

Presentation
表紙

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[Date]2007/5/3
[Paper #]
目次

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[Date]2007/5/3
[Paper #]
正誤表

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[Date]2007/5/3
[Paper #]
Memory Assignment Method for Matrix Processing Array

Akira KOBASHI,  Ittetsu TANIGUCHI,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  Kiyoshi NAKATA,  

[Date]2007/5/3
[Paper #]VLD2007-1
Heuristic Instruction Scheduling Method for Processors with Partial Forwarding Structure

Takuji HIEDA,  Hiroaki TANAKA,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2007/5/3
[Paper #]VLD2007-2
Reconfigurable Architecture with Calculation Function for Shift Keying

Ayataka KOBAYASHI,  Ittetsu TANIGUCHI,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2007/5/3
[Paper #]VLD2007-3
A Modeling for Dynamically Reconfigurable Processor using SystemC

Koji UEDA,  Junji KITAMICHI,  Kenichi KURODA,  

[Date]2007/5/3
[Paper #]VLD2007-4
An Architecture Design and its Evaluation for Speech Recognition System

Joe HASHIMOTO,  Makoto SAITSUJI,  Takashi KAMBE,  

[Date]2007/5/3
[Paper #]VLD2007-5
High-level synthesis; will it be useful or useless?

Masahiro FUKUI,  Nagisa ISHIURA,  Tomonori IZUMI,  Akihisa YAMADA,  

[Date]2007/5/3
[Paper #]VLD2007-6
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[Date]2007/5/3
[Paper #]
奥付

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[Date]2007/5/3
[Paper #]