Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2007/03/02)

Presentation
表紙

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[Date]2007/3/2
[Paper #]
目次

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[Date]2007/3/2
[Paper #]
Easily Testable Multiplier with 4-2 Adder Tree

Nobutaka KITO,  Kensuke HANAI,  Naofumi TAKAGI,  

[Date]2007/3/2
[Paper #]VLD2006-104,ICD2006-231
Effecto of the Number of Wiring Layers on the Chip Area of Multiplies

Hirotaka KAWASHIMA,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2007/3/2
[Paper #]VLD2006-141,ICD2006-232
A Combined Circuit for Multiplication and Inversion in GF(2^m) Based on the Extended Euclid's Algorithm

Katsuki KOBAYASHI,  Naofumi TAKAGI,  

[Date]2007/3/2
[Paper #]VLD2006-142,ICD2006-233
A study of high-speed projective transformation method

Yoshinori YAMADA,  Yasuhide KIMURA,  Daisuke ITO,  Tomoyuki YOKOGAWA,  Youichiro SATO,  Michiyosi HAYASE,  

[Date]2007/3/2
[Paper #]VLD2006-143,ICD2006-234
On an Optimality of a Sampling Circuit for Liquid Crystal Displays

Shingo Takahashi,  Shuji Tsukiyama,  Masanori Hashimoto,  Isao Shirakawa,  

[Date]2007/3/2
[Paper #]VLD2006-144,ICD2006-235
A Consideration of MPEG-A Photo player Meta-data Generation System Design with Hardware Acceleration for Mobile Devices

Masato MOTOHASHI,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/3/2
[Paper #]VLD2006-145,ICD2006-236
System LSI Architecture for Embedded Applications in Multi-Core era

Naohiko IRIE,  

[Date]2007/3/2
[Paper #]VLD2006-146,ICD2006-237
An Object Oriented System LSI Design Method Using Java Language

Seigo MASUOKA,  Hiroyuki TERAI,  Manabu KOYAMA,  Kazuhiko NAKAHARA,  Akihisa YAMADA,  Takashi KAMBE,  

[Date]2007/3/2
[Paper #]VLD2006-147,ICD2006-238
A Method to Evaluate Logic Functions Based On Decision Diagram Using Memory Packing

Hiroyuki TANAKA,  Hiroki NAKAHARA,  Munehiro MATSUURA,  Tsutomu SASAO,  

[Date]2007/3/2
[Paper #]VLD2006-148,ICD2006-239
Design Method of High Density System LSI with Three-Dimensional Transistor(FinFET) : Reduction of Pattern Area

Shigeyoshi Watanabe,  Keisuke Okamoto,  Makoto Oya,  

[Date]2007/3/2
[Paper #]VLD2006-149,ICD2006-240
A study of performance evaluation of Globally Asynchronous Locally Synchronous System

Kazuyuki TASHIRO,  Tomoyuki YOKOGAWA,  Isao KAYANO,  Youiciro SATO,  Michiyosi HAYASE,  

[Date]2007/3/2
[Paper #]VLD2006-150,ICD2006-241
Behavior level power modeling algorithm which considers area-speed tradeoff

Noriyuki INOUE,  Masaaki OHTSUKI,  Masahiro FUKUI,  

[Date]2007/3/2
[Paper #]VLD2006-151,ICD2006-242
An efficient battery modeling and optimization for battery driven systems

Sayaka IWAKOSHI,  Yu CHIKAYAMA,  Masahiro FUKUI,  

[Date]2007/3/2
[Paper #]VLD2006-152,ICD2006-243
Design method of low-power dual-supply-voltage system LSI taking into account gate/sub-threshold leakage current of MOSFET

Shigeyoshi Watanabe,  Satoshi Hanami,  Manabu Kobayashi,  Toshitoku Takabatake,  

[Date]2007/3/2
[Paper #]VLD2006-153,ICD2006-244
Analysis for factors that affect power dissipation for Multiplier applying Run Time Power Gating

Seidai TAKEDA,  Toshihiro KASHIMA,  Toshiaki SHIRAI,  Naoaki OHKUBO,  Kimiyoshi USAMI,  

[Date]2007/3/2
[Paper #]VLD2006-154,ICD2006-245
Characteristic of Random Curved Surface and a Proposition of a New Curved Surface Model : An Universal Random Curved Surface Model Formed from Rotational Gaussians

Shin-ichi OHKAWA,  Hiroo MASDA,  

[Date]2007/3/2
[Paper #]VLD2006-155,ICD2006-246
Statictical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations

Katsumi HOMMA,  Izumi NITTA,  Toshiyuki SHIBUYA,  

[Date]2007/3/2
[Paper #]VLD2006-156,ICD2006-247
Sequence-Pair Based Compaction under Crosstalk Constraint

Tetsuya TASHIRO,  Takehiko MATSUO,  Shigetoshi NAKATAKE,  

[Date]2007/3/2
[Paper #]VLD2006-157,ICD2006-248
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