Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2007/03/01)

Presentation
表紙

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[Date]2007/3/1
[Paper #]
目次

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[Date]2007/3/1
[Paper #]
A Processing Unit Optimization Algorithm in SIMD Processor Cores Design

Hiroyuki SHIGETA,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/3/1
[Paper #]VLD2006-119,ICD2006-210
A Hardware/Software Partitioning Framework for SIMD Processor Cores

Masataka OHIGASHI,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/3/1
[Paper #]VLD2006-120,ICD2006-211
SIMD Instructions Generation Algorithm for Multi Loop for SIMD Processor Cores Optimum Design

Hiroki NAKAJIMA,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/3/1
[Paper #]VLD2006-121,ICD2006-212
A Data Cache Optimization System for Application Processor Cores and Its Experimental Evaluations

Kazuhisa HORIUCHI,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2007/3/1
[Paper #]VLD2006-122,ICD2006-213
An deeicien design methodology for digital system of image processing by high level description language

Satoru INOUE,  Taiki HASHIZUME,  Tomonori IZUMI,  Masahiro FUKUI,  

[Date]2007/3/1
[Paper #]VLD2006-123,ICD2006-214
Mixed Analog-Digital Fully-parallel Associative Memory with Differential Amplifier

Yuki TANAKA,  Md. Anwarul ABEDIN,  Tetsushi KOIDE,  Hans Juergen MATTAUSCH,  

[Date]2007/3/1
[Paper #]VLD2006-124,ICD2006-215
A 90-nm SRAM for Video Signal processors implementing Dynamic Voltage and Frequency Scaling

Takeshi Iwanari,  Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2007/3/1
[Paper #]VLD2006-125,ICD2006-216
A Clock Deskew Method Using Statistical Presumption

Naoki OTANI,  Yuko HASHIZUME,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2007/3/1
[Paper #]VLD2006-126,ICD2006-217
A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits

Yousuke HARADA,  Hiroyoshi HASHIMOTO,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2007/3/1
[Paper #]VLD2006-127,ICD2006-218
Low Power and High Speed Clock Distribution Technique fo 90-nm CMOS LSIs

Yousuke Hahiwara,  Suguru Nagayama,  Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2007/3/1
[Paper #]VLD2006-128,ICD2006-219
The Potential Router

Yoji KAJITANI,  

[Date]2007/3/1
[Paper #]VLD2006-129,ICD2006-220
Escape Fitting between a Pair of Pin-sets

Masato INAGI,  Yasuhiro TAKASHIMA,  Yoji KAJITANI,  

[Date]2007/3/1
[Paper #]VLD2006-130,ICD2006-221
BGA Routing by The Potential Router

Takayuki HIROMATSU,  Masato INAGI,  Yasuhiro TAKASHIMA,  Yoji kAJITANI,  

[Date]2007/3/1
[Paper #]VLD2006-131,ICD2006-222
Automatic routing methods to make it easy to modify after routing

Toshihiko YOKOMARU,  Takahide YOSHIKAWA,  Yuzi KANAZAWA,  

[Date]2007/3/1
[Paper #]VLD-2006-132,ICD2006-223
Relocation Method for Circuit Modification

Kunihiko YANAGIBASHI,  Yasuhiro TAKASHIMA,  Yuichi NAKAMURA,  

[Date]2007/3/1
[Paper #]VLD2006-133,ICD2006-224
A CAM Emulator Using Look-Up Table Cascades

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2007/3/1
[Paper #]VLD2006-134,ICD2006-225
Design Method of Radix Converters Using Arithmetic Decompositions(3)

Yukihiro IGUCHI,  Tsutomu SASAO,  Munehiro MATSUURA,  Toshikazu AOYAMA,  

[Date]2007/3/1
[Paper #]VLD2006-135,ICD2006-226
Design of RSA Encryption circuit with embedded Fixed Private Key using Via Programmable Logic VPEX

Hiroshi Shimomura,  Kazuki Okuyama,  Akihiro Nakamura,  Takeshi Fujino,  

[Date]2007/3/1
[Paper #]VLD2006-136,ICD2006-227
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