Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2006/09/19)

Presentation
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[Date]2006/9/19
[Paper #]
目次

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[Date]2006/9/19
[Paper #]
A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory

Akihiko TSUKAHARA,  Akinori KANASUGI,  

[Date]2006/9/19
[Paper #]VLD2006-39,SDM2006-160
3D Atomistic Density Gradient Device Simulation Considering Random Doping Induced Fluctuations for MOSFETs

Yoshio ASHIZAWA,  Hideki OKA,  

[Date]2006/9/19
[Paper #]VLD2006-40,SDM2006-161
Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation

Katsumi EIKYU,  Takeshi OKAGAKI,  Motoaki TANIZAWA,  Kiyoshi ISHIKAWA,  Osamu TSUCHIYA,  

[Date]2006/9/19
[Paper #]VLD2006-41,SDM2006-162
Modeling of Discrete Dopant Effects on Threshold Voltage Shift by Random Telegraph Signal

Ken'ichiro SONODA,  Kiyoshi ISHIKAWA,  Takahisa EIMORI,  Osamu TSUCHIYA,  

[Date]2006/9/19
[Paper #]VLD2006-42,SDM2006-163
Improvement of Drive Current in Bulk-FinFET using Full 3-D Process/Device Simulations

Takahisa KANEMURA,  Takashi IZUMIDA,  Nobutoshi AOKI,  Masaki KONDO,  Sanae ITO,  Toshiyuki ENDA,  Kimitoshi OKANO,  Hirohisa KAWASAKI,  Atsushi YAGISHITA,  Akio KANEKO,  Satoshi INABA,  Mitsutoshi NAKAMURA,  Kazunari ISHIMARU,  Kyoichi SUGURO,  Kazuhiro EGUCHI,  Hidemi ISHIUCHI,  

[Date]2006/9/19
[Paper #]VLD2006-43,SDM2006-164
Analysis of Underlapped Single-Gate Ultrathin SOI MOSFET with High-k Gate Dielectric : characteristic advancement and suppression of dispersion

Yoshimasa YOSHIOKA,  Yasuhisa OMURA,  

[Date]2006/9/19
[Paper #]VLD2006-44,SDM2006-165
A Novel Asymmetric Raised Source/Drain Extension Structure for 32nm-node MOSFETs : An Ultimate Planar MOSFET

Tsutomu IMOTO,  Yasushi TATESHITA,  Toshio KOBAYASHI,  

[Date]2006/9/19
[Paper #]VLD2006-45,SDM2006-166
Empirical Models of Phonon-Limited Electron Mobility for Ultra-Thin Body Single-Gate and Double-Gate SOI MOSFETs with (001) or (111) Si Surface Channel

Tsuyoshi YAMAMURA,  Shingo SATO,  Yasuhisa OMURA,  

[Date]2006/9/19
[Paper #]VLD2006-46,SDM2006-167
Ballistic Transport in Nanoscale MOSFETs

Hideaki TSUCHIYA,  Kazuya FUJII,  Takashi Mori,  Tanroku MIYOSHI,  

[Date]2006/9/19
[Paper #]VLD2006-47,SDM2006-168
Quantum Transport Simulation of Ballistic Current in Silicon Nanostructures with a Strained Layer

Hideki MINARI,  Nobuya MORI,  

[Date]2006/9/19
[Paper #]VLD2006-48,SDM2006-169
Quantum Electron Transport Modeling in Nano-Scale Devices Based on Multiband Non-Equilibrium Green's Function Method

Helmy FITRIAWAN,  Satofumi SOUMA,  Matsuto OGAWA,  Tanroku MIYOSHI,  

[Date]2006/9/19
[Paper #]VLD2006-49,SDM2006-170
Self-consistent full-band Monte Carlo device simulation for strained nMOSFETs incorporating vertical quantization, multi-subband, and different channel orientation effects

Masami HANE,  Takeo IKEZAWA,  MIichihito KAWADA,  Tatsuya EZAKI,  Toyoji YAMAMOTO,  

[Date]2006/9/19
[Paper #]VLD2006-50,SDM2006-171
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[Date]2006/9/19
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[Date]2006/9/19
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[Date]2006/9/19
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