Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2006/05/05)

Presentation
表紙

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[Date]2006/5/5
[Paper #]
目次

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[Date]2006/5/5
[Paper #]
Bottom-up equivalence checking for SpecC programs

Subash SHANKAR,  Masahiro FUJITA,  

[Date]2006/5/5
[Paper #]VLD2006-6
An Approach to Equivalence Checking by Symbolic Simulation between Behavioral and RTL Designs

Takeshi MATSUMOTO,  Satoshi KOMATSU,  Masahiro FUJITA,  

[Date]2006/5/5
[Paper #]VLD2006-7
An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel

Takatomi WADA,  Yasushi HIBINO,  

[Date]2006/5/5
[Paper #]VLD2006-8
Efficient generation method of indirect implication on ATPG

Masayoshi YOSHIMURA,  Seiji KAJIHARA,  Yusuke MATSUNAGA,  

[Date]2006/5/5
[Paper #]VLD2006-9
Power-Conscious Microprocessor-Based Testing of System-on-Chip

Fawnizu Azmadi Hussin,  Tomokazu Yoneda,  Alex Orailoglu,  Hideo Fujiwara,  

[Date]2006/5/5
[Paper #]VLD2006-10
Reduction of Equalizing Circuit Area for 8-VSB Demodulator Using the Result of Correlation Operation

Kazumi KAWASHIMA,  Yusuke KONISHI,  Yusuke HASHIGUCHI,  Yuu YAMAMOTO,  Masahiro NUMA,  

[Date]2006/5/5
[Paper #]VLD2006-11
Delay and Power Consumption of Integer Multiplier : Comparison of Wallace and Dadda tree

Masayoshi TACHIBANA,  

[Date]2006/5/5
[Paper #]VLD2006-12
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits

Masaki YAMAGUCHI,  Yang YUAN,  Kosuke TARUMI,  Ryota SAKAMOTO,  Masanori MUROYAMA,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]2006/5/5
[Paper #]VLD2006-13
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[Date]2006/5/5
[Paper #]
Notice about photocopying

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[Date]2006/5/5
[Paper #]
奥付

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[Date]2006/5/5
[Paper #]