Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2005/11/25)

Presentation
表紙

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[Date]2005/11/25
[Paper #]
目次

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[Date]2005/11/25
[Paper #]
On Low Capture Power Test Generation for Scan Testing

Tatsuya SUZUKI,  Xiaoqing WEN,  Seiji KAJIHARA,  Kohei MIYASE,  Yoshihiro MINAMOTO,  

[Date]2005/11/25
[Paper #]VLD2005-76,ICD2005-171,DC2005-53
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits

Tsuyoshi IWAGAKI,  Satoshi OHTAKE,  Hideo FUJIWARA,  

[Date]2005/11/25
[Paper #]VLD2005-77,ICD2005-172,DC2005-54
A Note on Expansion of Convolutional Compactors over Galois Field

Masayuki ARAI,  Satoshi FUKUMOTO,  Kazuhiko IWASAKI,  

[Date]2005/11/25
[Paper #]VLD2005-78,ICD2005-173,DC2005-55
Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP

Kenichi NISHIGUCHI,  Nagisa ISHIURA,  Masanari NISHIMURA,  Hiroyuki KANBARA,  Hiroyuki TOMIYAMA,  Yutetsu TAKATSUKASA,  Manabu KOTANI,  

[Date]2005/11/25
[Paper #]VLD2005-79,ICD2005-174,DC2005-56
A Cycle Budgeting Method for Tasks and Bus Transfers of Bus Systems Using Scenarios

Seiji YAMAGUCHI,  Tadaaki TANIMOTO,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2005/11/25
[Paper #]VLD2005-80,ICD2005-175,DC2005-57
C-Based design of a Real-time Particle Tracking System

Kenichi JYOKO,  Takahiro OHGUCHI,  Hirokazu UETU,  Koji SAKAI,  Takanori OHKURA,  Takashi KAMBE,  

[Date]2005/11/25
[Paper #]VLD2005-81,ICD2005-176,DC2005-58
Examinations of Small-World and Scale-Free characteristics in logic circuits

Toshiaki MIYAZAKI,  

[Date]2005/11/25
[Paper #]VLD2005-82,ICD2005-177,DC2005-59
Exact Minimum Logic Factoring via Quantified Boolean Satisfiability

Hiroaki YOSHIDA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2005/11/25
[Paper #]VLD2005-83,ICD2005-178,DC2005-60
An Encoding Method for Rail Outputs in LUT Cascade Emulators

Shinya NAGAYASU,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2005/11/25
[Paper #]VLD2005-84,ICD2005-179,DC2005-61
A Logic Simulation using an Look-Up Table Cascade Emulator

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2005/11/25
[Paper #]VLD2005-85,ICD2005-180,DC2005-62
Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis

Tomohiro YONEDA,  Chris MYERS,  

[Date]2005/11/25
[Paper #]VLD2005-86,ICD2005-181,DC2005-63
Structural Coverage of Traversed Transitions for Symbolic Model Checking

Xingwen Xu,  Shinji Kimura,  Kazunari Horikawa,  Takehiko Tsuchiya,  

[Date]2005/11/25
[Paper #]VLD2005-87,ICD2005-182,DC2005-64
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[Date]2005/11/25
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[Date]2005/11/25
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[Date]2005/11/25
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