Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2005/05/13)

Presentation
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[Date]2005/5/13
[Paper #]
目次

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[Date]2005/5/13
[Paper #]
A Placement Optimization by Simulated Annealing using Various Cooling Schedules

Kazuyuki Tanabe,  Masahiko Toyonaga,  

[Date]2005/5/13
[Paper #]VLD2005-6
A Multi-Layer Incremental Router for Layout Design with Fewer Layers

Shigeru Takenaga,  Masahiko Toyonaga,  

[Date]2005/5/13
[Paper #]VLD2005-7
An algorithm to calculate the minimum clock period of a semi-synchronous circuit that contains multi-clock cycle path

BakhtiarAffendi ROSDI,  Atsushi TAKAHASHI,  

[Date]2005/5/13
[Paper #]VLD2005-8
Architecture Level Design Quality Estimation Method based on Data Flow Analysis

Noboru YONEOKA,  Kyoko UEDA,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2005/5/13
[Paper #]VLD2005-9
Equivalence Checking for C Description by Local Symbolic Simulation Using Dependence Graphs

Takeshi MATSUMOTO,  Hiroshi SAITO,  Masahiro FUJITA,  

[Date]2005/5/13
[Paper #]VLD2005-10
A LED Display with Serial Control of Sub-frame Lighting Data

Fumitaka TANIWAKI,  Daisuke YAMAOKA,  Seiken YANO,  

[Date]2005/5/13
[Paper #]VLD2005-11
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[Date]2005/5/13
[Paper #]
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[Date]2005/5/13
[Paper #]
奥付

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[Date]2005/5/13
[Paper #]