Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2005/01/19)

Presentation
表紙

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[Date]2005/1/19
[Paper #]
目次

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[Date]2005/1/19
[Paper #]
Preliminary Implementation of Volume Rendering Circuit onto an FPGA-based Visualization Accelerator

Dai OKAMURA,  Masahiro GOSHIMA,  Shinichiro MORI,  Yasuhiko NAKASHIMA,  Shinji TOMITA,  

[Date]2005/1/19
[Paper #]VLD2004-110,CPSY2004-76
Hardware Realization of Panoramic Image Generation Function

Yukinori NAGASE,  Takao KAWAMURA,  Kazunori SUGAHARA,  

[Date]2005/1/19
[Paper #]VLD2004-111,CPSY2004-77
Hardware Realization of Active Contour Model and Its Application for Vowel Recognition by Lip Reading

Yusuke SASAKI,  Takao KAWAMURA,  Kazunori SUGAHARA,  

[Date]2005/1/19
[Paper #]VLD2004-112,CPSY2004-78
FPGA-based Sound Analysis System for the Marine Organism

Yuki SHIMIZU,  Rajendar BAHL,  Masao SAKATA,  Tamaki URA,  Masao YANAGISAWA,  

[Date]2005/1/19
[Paper #]VLD2004-113,CPSY2004-79
Detection of the audio watermark on FPGA

Kazuhiro SAKAKIBARA,  Yasushi INOGUCHI,  

[Date]2005/1/19
[Paper #]VLD2004-114,CPSY2004-80
Configurable Processor MeP and its SoC Design Examples

Takashi Miyamori,  

[Date]2005/1/19
[Paper #]VLD2004-115,CPSY2004-81
Design and Development of Microprocessors on a Hardware/Software Co-learning System

Koichiro NAKAMURA,  Hoang Anh TUAN,  Shigeru OYANAGI,  Katsuhiro YAMAZAKI,  

[Date]2005/1/19
[Paper #]VLD2004-116,CPSY2004-82
Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY

Akio KAMIMURAI,  Ryotaro KOBAYASHI,  Hideki ANDO,  Toshio SHIMADA,  

[Date]2005/1/19
[Paper #]VLD2004-117,CPSY2004-83
ASIP Architecture for Real-Time Graphical Effect Processing

Tatsuhiro YOSHIMURA,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2005/1/19
[Paper #]VLD2004-118,CPSY2004-84
Extraction of Instruction Latency from Cycle-True Processor Models

Yusuke HIRAOKA,  Nagisa ISHIURA,  Masaharu IMAI,  

[Date]2005/1/19
[Paper #]VLD2004-119,CPSY2004-85
Instruction Pattern Generation for Retargetable Compiler

Atsushi KISHIMOTO,  Nagisa ISHIURA,  Yuuki MASUI,  Masaharu IMAI,  

[Date]2005/1/19
[Paper #]VLD2004-120,CPSY2004-86
Proposal and Implementation of Framework for Self-Reproductive Applications on Dynamically Reconfigurable Device PCA

Tomoki KAMIYAMA,  Keigo KURATA,  Yousuke IKEHATA,  Junji KITAMICHI,  Kenichi KURODA,  

[Date]2005/1/19
[Paper #]VLD2004-121,CPSY2004-87
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring

Hui QIN,  Tsutomu SASAO,  Yukihiro IGUCHI,  

[Date]2005/1/19
[Paper #]VLD2004-122,CPSY2004-88
Residue-to-Weighted Converter Using Signed-Digit Number Arithmetic

Yumi OGAWA,  Shuangching CHEN,  Shugang WEI,  

[Date]2005/1/19
[Paper #]VLD2004-123,CPSY2004-89
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[Date]2005/1/19
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