Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2005/01/18)

Presentation
表紙

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[Date]2005/1/18
[Paper #]
目次

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[Date]2005/1/18
[Paper #]
A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection

Makoto OKADA,  Tatsuo HIRAMATSU,  Hiroshi NAKAJIMA,  Makoto OZONE,  Katsunori HIRASE,  Shinji KIMURA,  

[Date]2005/1/18
[Paper #]VLD2004-97,CPSY2004-63
Reconfigurable 1-bit processor array with reduced wiring area

Nobuo NAKAI,  Masaki NAKANISHI,  Shigeru YAMASHITA,  Katsumasa WATANABE,  

[Date]2005/1/18
[Paper #]VLD2004-98,CPSY2004-64
A context dependent clock control mechanism for dynamically reconfigurable processors

Hideharu AMANO,  Yoshinori ADACHI,  Satoshi TSUTSUMI,  Kenichiro ISHIKAWA,  

[Date]2005/1/18
[Paper #]VLD2004-99,CPSY2004-65
An asynchronous multi-context device with new context switching method

Yoshinori ADACHI,  Satoshi TSUTSUMI,  Hideharu AMANO,  

[Date]2005/1/18
[Paper #]VLD2004-100,CPSY2004-66
A Discussion on Fault Tolerance of Dynamic Reconfigurable Device

Naoki OCHI,  Kentaro NAKAHARA,  Futoshi MORIE,  Shinichi KOUYAMA,  Tomonori IZUMI,  Hiroyuki OCHI,  Yukihiro NAKAMURA,  

[Date]2005/1/18
[Paper #]VLD2004-101,CPSY2004-67
Basics and Aims of Assertion-Based Verification

Kiyoharu HAMAGUCHI,  

[Date]2005/1/18
[Paper #]VLD2004-102,CPSY2004-68
Verification IP and Assertion for IP-Reuse promotion : Verification IP and the related activities in STARC

Masanori Imai,  

[Date]2005/1/18
[Paper #]VLD2004-103,CPSY2004-69
A Dividing Technique of Assertions for an Interface Protocol used in a Divide and Conquer Approach of Formal Verification

Hironao MATSUSHIMA,  Akira KITAJIMA,  

[Date]2005/1/18
[Paper #]VLD2004-104,CPSY2004-70
A novel Placement Procedure for crosstalk noise

Masakazu OCHIAI,  Masaya YOSHIKAWA,  Takeshi FUJINO,  Hidekazu TERAI,  

[Date]2005/1/18
[Paper #]VLD2004-105,CPSY2004-71
An Instance-Specific Hardware Algorithm Using FPGAs for the Mimimum Vertex Cover Problem of a Graph

Kenji KIKUCHI,  Shinichi WAKABAYASHI,  

[Date]2005/1/18
[Paper #]VLD2004-106,CPSY2004-72
Solving SAT problems by PCMGTP on FPGA

Shohei KINOSHITA,  Junichi MATSUDA,  Hiroshi FUJITA,  Miyuki KOSHIMURA,  Ryuzo HASEGAWA,  

[Date]2005/1/18
[Paper #]VLD2004-107,CPSY2004-73
Design of cellular simulation platform for SBML model

Yow Iwaoka,  Yasunori Osana,  Tomonori Fukushima,  Masato Yoshimi,  Akira Hunahashi,  Noriko Hiroi,  Yuichiro Shibata,  Naoki Iwanaga,  Hiroaki Kitano,  Hideharu Amano,  

[Date]2005/1/18
[Paper #]VLD2004-108,CPSY2004-74
Architecture for crossover operation based on sequence pair

Ryousuke Knamitsu,  Akinori Bito,  Masaya Yoshikawa,  Hidekazu Terai,  

[Date]2005/1/18
[Paper #]VLD2004-109,CPSY2004-75
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[Date]2005/1/18
[Paper #]