Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2004/01/15)

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[Date]2004/1/15
[Paper #]
目次

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[Date]2004/1/15
[Paper #]
Reconfigurable Interconnection and Its Application to the Bit-Exchange Unit in a Processor

Yasunori HARADA,  Shinji KIMURA,  Masao YANAGISAWA,  

[Date]2004/1/15
[Paper #]VLD2003-114,CPSY2003-23
Performance Evaluation of a Resource-Shared VLIW Processor Array

Masao ARAMOTO,  Yoichi YUYAMA,  Akihiko HIGUCHI,  Junka OKAZAWA,  Kazutoshi KOBAYASHI,  Hidetoshi ONODERA,  

[Date]2004/1/15
[Paper #]VLD2003-115,CPSY2603-24
Research on optimization of the processor structure for DCT

Atsushi Sekine,  Gensuke Goto,  Jube Tada,  

[Date]2004/1/15
[Paper #]VLD2003-116,CPSY2003-25
Design of Producer-order Parallel Queue Processor Architecture

Arsenij MARKOVSKIJ,  Masahiro SOWA,  Ben ABDERAZEK,  Soichi SHIGETA,  Tsutomu YOSHINAGA,  

[Date]2004/1/15
[Paper #]VLD2003-117,CPSY2003-26
C Compiler for Dynamically Reconfigurable Processor: DRP

Toru AWASHIMA,  Takao TOI,  Noritsugu NAKAMURA,  Hirokazu KAMI,  Yoshinosuke KATO,  Kazutoshi WAKABAYASHI,  Yoshiyuki MIYAZAWA,  JING Li,  

[Date]2004/1/15
[Paper #]VLD2003-118,CPSY2003-27
The Implementation of The Block Cipher RC6 on The Reconfigurable Processor

Yohei HASEGAWA,  Yutaka YAMADA,  Katsuaki DEGUCHI,  Kenichiro ANJO,  Toru AWASHIMA,  Hideharu AMANO,  

[Date]2004/1/15
[Paper #]VLD2003-119,CPSY2003-28
Implementation of Anti-aliasing Alpha Blender on the Reconfigurable Processor DRP

Masayasu SUZUKI,  Yutaka YAMADA,  Katsuaki DEGUCHI,  Kenichiro ANJO,  Toru AWASHIMA,  Hideharu AMANO,  

[Date]2004/1/15
[Paper #]VLD2003-120,CPSY2003-29
Function Offloader for DRP

Takeshi INUO,  Kengo NISHINO,  Shogo NAKAYA,  Nobuki Kajihara,  Hirokazu KAMI,  Takao TOI,  Toru AWASHIMA,  

[Date]2004/1/15
[Paper #]VLD2003-121,CPSY2003-30
A Virtual Hardware mechanism on DRP

Hideharu AMANO,  Takeshi INUO,  Hirokazu KAMI,  

[Date]2004/1/15
[Paper #]VLD2003-122,CPSY2003-31
Proposal of N-dimensional Fast Hadamard Transform Algorithm and Implementation on Dynamically Reconfigurable Device

Hiroaki TAKAHASHI,  Junji KITAMICHI,  Kenichi KURODA,  

[Date]2004/1/15
[Paper #]VLD2003-123,CPSY2003-32
A Design Scheme for Data Driven Circuits on PCA-Chip2

Naoki OCHI,  Takafumi YUASA,  Tomonori IZUMI,  Takao ONOYE,  Yukihiro NAKAMURA,  

[Date]2004/1/15
[Paper #]VLD2003-124,CPSY2003-33
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[Date]2004/1/15
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[Date]2004/1/15
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