Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2002/01/17)

Presentation
表紙

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[Date]2002/1/17
[Paper #]
目次

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[Date]2002/1/17
[Paper #]
Testbed System for Reconfigurable Coprocessing Systems

Yuusuke KAZU,  Takanori HAYASHIDA,  Kazuaki MURAKAMI,  

[Date]2002/1/17
[Paper #]2001-VLD-132,2001-CPSY-91
PCI Interface by FPGA of Hardware and Software heterogeneous system : The format of Technical Report

Yusuke SHIGA,  Haruki IMANAKA,  Takashi UENO,  Kenji KUDO,  Masatosi SEKINE,  

[Date]2002/1/17
[Paper #]2001-VLD-133,2001-CPSY-92
Consideration on Tradeoff for Performance/Area of Exponential Function Circuits

Hidenori HATAE,  Koji HASHIMOTO,  Kazuaki MURAKAMI,  

[Date]2002/1/17
[Paper #]2001-VLD-134,2001-CPSY-93
Size/Position detection algorithm on The Visual Device

Yoshiaki AJIOKA,  Masahiro SHIMADA,  Hideharu AMANO,  

[Date]2002/1/17
[Paper #]2001-VLD-135,2001-CPSY-94
VLSI Architecture for MPEG-4 Core Profile Video Codec

Takashi NAKAGAWA,  Shinsuke HAMANAKA,  YUN HE Xiao,  Gen FUJITA,  Isao SHIRAKAWA,  

[Date]2002/1/17
[Paper #]2001-VLD-136,C2001-CPSY-95
Implementation of Java Execution Environment for Embedded Systems

Motoki KIMURA,  Morgan Hirosuke MIKI,  Takao ONOYE,  Isao SHIRAKAWA,  

[Date]2002/1/17
[Paper #]2001-VLD-137,2001-CPSY-96
On Delay Minimum Mapping Algorithm for FPGAs Using Boolean Matching

Yusuke MATSUNAGA,  

[Date]2002/1/17
[Paper #]2001-VLD-138,2001-CPSY-97
An Algorithm of Minimizing AND-EXOR Expressions

Takashi HIRAYAMA,  Yasuaki NISHITANI,  

[Date]2002/1/17
[Paper #]2001-VLD-139,2001-CPSY-98
Networks Based on Pseudoproduct and its Testability

Ryoji ISHIKAWA,  Tomonori IGARASHI,  Takashi HIRAYAMA,  Kensuke SHIMIZU,  

[Date]2002/1/17
[Paper #]2001-VLD-140,2001-CPSY-99
A Fast Method to Evaluate Multiple-Output Logic Functions using BDDs

Munchiro MATSUURA,  Yukihiro IGUCHI,  Tsutomu SASAO,  

[Date]2002/1/17
[Paper #]2001-VLD-141,2001-CPSY-100
Representations of Logic Functions using QRMDDs

Shinobu NAGAYAMA,  Tsutomu SASAO,  Yukihiro IGUCHI,  Munehiro MATSUURA,  

[Date]2002/1/17
[Paper #]2001-VLD-142,2001-CPSY-101
RTL Optimization and Physical Implementation Methodology in Deep Sub-Micron Design

Satoshi TAKASHIMA,  Kozo KIMURA,  Tokuzo KIYOHARA,  Toshiyuki OCHIAI,  

[Date]2002/1/17
[Paper #]2001-VLD-143,2001-CPSY-102
A High-Level Power Optimization Algorithm for System VLSIs Based on Area/Delay/Power Estimation

Shinichi NODA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2002/1/17
[Paper #]2001-VLD-144,2001-CPSY-103
A Compiler Generation Method in The PEAS-III System and Its Evaluation

Shinsuke KOBAYASHI,  Kentaro MITA,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2002/1/17
[Paper #]2001-VLD-145,2001-CPSY-104
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[Date]2002/1/17
[Paper #]