IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2001/06/22)

Presentation

表紙

[Date]2001/6/22
[Paper #]

A Design of Filter Banks Using Genetic Algorithm

Fumio ITAMI, Eiji WATANABE, Akinori NISHIHARA,

[Date]2001/6/22
[Paper #]CAS2001-29,VLD2001-46,DSP2001-48

A Design of Stack Filters Using Genetic Programming

Noriyuki MAO, Masayuki KAWAMATA,

[Date]2001/6/22
[Paper #]CAS2001-30,VLD2001-47,DSP2001-49

A Study on Improvement of Convergence Rate of Adaptive Notch Filter

Yoshio ITOH, Masaki NAKAO, James Okello, Yutaka FUKUI, Masaki KOBAYASHI,

[Date]2001/6/22
[Paper #]CAS2001-31,VLD2001-48,DSP2001-50

A Gradient Adaptive Lattice Filter Algorithm for Efficient CORDIC Implementation

Shinichi Shiraishi, Miki Haseyama, Hideo Kitajima,

[Date]2001/6/22
[Paper #]CAS2001-32,VLD2001-49,DSP2001-51

Design of a Parallel and Concurrent LSI System for Hidden Markov Models

Shingo YOSHIZAWA, Yoshikazu MIYANAGA, Norinobu YOSHIDA,

[Date]2001/6/22
[Paper #]CAS2001-33,VLD2001-50,DSP2001-52

Flexible structure LSI of PCA.

Wichai Boonkumklao, Yoshikazu Miyanaga, Kobchai Dejhan,

[Date]2001/6/22
[Paper #]CAS2001-34,VLD2001-51,DSP2001-53

A Note on an FPGA Design of a Motion Estimator

Kazushi Nakagawa, Shinichi Shiraishi, Miki Haseyama, Hideo Kitajima,

[Date]2001/6/22
[Paper #]CAS2001-35,VLD2001-52,DSP2001-54

An Overview of Bluetooth SIG 1.0 Specification and introduction of Bluetooth SIG 2.0 status

Yoshinari KUMAKI,

[Date]2001/6/22
[Paper #]CAS2001-36,VLD2001-53,DSP2001-55

Module Placement for Safe Routing using Sequence-Pair

Takashi NOJIMA, Keishi SAKANUSHI, Atsushi TAKAHASHI, Yoji KAJITANI,

[Date]2001/6/22
[Paper #]CAS2001-37,VLD2001-54,DSP2001-56

Modeling of Placement Cost Function for Super-cell

Toshiro Akino,

[Date]2001/6/22
[Paper #]CAS2001-38,VLD2001-55,DSP2001-57

A Pipelined Scheduling Method Considering Conditional Branches

Makoto IKENAGA, Katsumi HARASHIMA, Toshirou KUTSUWA,

[Date]2001/6/22
[Paper #]CAS2001-31,VLD2001-56,DSP2001-58

IEEE1394 Hardware/Software Co-simulation environment and design of its Link layer controller

Hirofumi Yamamoto, Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura,

[Date]2001/6/22
[Paper #]CAS2001-40,VLD2001-57,DSP2001-59

VLSI Implementation or High Performance Burst Mode for 128-bit Block Ciphers

Yukio MITSUYAMA, Zaldy ANDALES, Takao ONOYE, Isao SHIRAKAWA,

[Date]2001/6/22
[Paper #]CAS2001-41,VLD2001-58,DSP2001-60

An Algorithm for Division on Finite Fields Based on Stein's Algorithm

Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi,

[Date]2001/6/22
[Paper #]CAS2001-42,VLD2001-59,DSP2001-61

Design and FPGA Implementation of a Parallel Structure of Evolutionary Digital Filters for Hardware Implementation

Naoyuki TSUSHIMA, Mari FUKUZAKI, Masahide ABE, Masayuki KAWAMATA,

[Date]2001/6/22
[Paper #]CAS2001-43,VLD2001-60,DSP2001-62

A study of time-Varying AR modeling by using linear approximation

Kiyohumi KONDO, Atsushi NAKAGAKI, Yoshikazu MIYANAGA,

[Date]2001/6/22
[Paper #]CAS2001-44,VLD2001-61,DSP2001-63

A Study of Spectrum Estimation of High Pitch Frequency Speech

Naoki Imagawa, Atsushi Nakagaki, Yoshikazu Miyanaga, Norinobu Yoshida,

[Date]2001/6/22
[Paper #]CAS2001-45,VLD2001-62,DSP2001-64

A Speech Feature Extraction Method via Time-Frequency Distribution

Kazuki NAKADA, Yoshikazu MIYANAGA, Tateo SHIMOZAWA,

[Date]2001/6/22
[Paper #]CAS2001-46,VLD2001-63,DSP2001-65