Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2000/09/14)

Presentation
表紙

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[Date]2000/9/14
[Paper #]
目次

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[Date]2000/9/14
[Paper #]
Three-dimensional Capacitance Analysis of an SRAM Cell

Yoshiaki Takemura,  Ken-ichi Osada,  Masayoshi Yagyu,  Ken Yamaguchi,  Jiro Ushio,  Takuya Maruizumi,  

[Date]2000/9/14
[Paper #]VLD2000-48,SDM2000-121
Characterization of Interconnect Coupling Noise using In-situ Delay-Change Curve Measurements

Takashi Sato,  Yu Cao,  Dennis Sylvester,  Chenming Hu,  

[Date]2000/9/14
[Paper #]VLD2000-49,SDM2000-122
New Method of Extracting Inductance from VLSI Circuit and Simulation with This Method

Y Nakashima,  K Ikeda,  K Asada,  

[Date]2000/9/14
[Paper #]VLD2000-50,SDM2000-123
Clock Tree Synthesis for Shrinking a Chip Design

Hiroaki INOUE,  Masato Edahiro,  

[Date]2000/9/14
[Paper #]VLD2000-51,SDM2000-124
A more accurate skew model for well-balanced H-tree clock distribution network

Xiaohong Jiang,  Susumu Horiguchi,  

[Date]2000/9/14
[Paper #]VLD2000-52,SDM2000-125
A System Generating SPICE Parameters to Estimate Fluctuation of Circuit Performance.

Makoto Kidera,  Motoaki Tanizawa,  Kenichiro Sonoda,  Kiyoshi Ishikawa,  Norihiko Kotani,  Masahide Inuishi,  

[Date]2000/9/14
[Paper #]VLD2000-53,SDM2000-126
A Method of Worst-Case Analysis for Process Fluctuation induced Circuit Characteristics Varistions

Tetsuya Yamaguchi,  

[Date]2000/9/14
[Paper #]VLD2000-54,SDM2000-127
Recognition of Layout by Parametric BSG for Reuse of Layout Design

Zhonglin Wu,  Keishi SAKANUSHI,  Yoji KAJITANI,  

[Date]2000/9/14
[Paper #]VLD2000-55,SDM2000-128
A Floorplan method based on the boundary method and genetic algorithm

Jin TAKAHASHI,  Akinori KANASUGI,  Kenji OHSHIMA,  

[Date]2000/9/14
[Paper #]VLD2000-56,SDM2000-129
[OTHERS]

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[Date]2000/9/14
[Paper #]