Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2000/01/12)

Presentation
表紙

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[Date]2000/1/12
[Paper #]
目次

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[Date]2000/1/12
[Paper #]
CPLD design by A High-Level Synthesis System

Shin Nakajyo,  Hiroshi Kawakami,  Ryo Dang,  

[Date]2000/1/12
[Paper #]VLD99-97,CPSY99-106
A Selected Mutation on Genetic Algorithm for the Floorplan Design Problem

Kosuke Funabori,  Ryo Dang,  

[Date]2000/1/12
[Paper #]VLD99-98,CPSY99-107
Gate Level Simulation of JK Flip-flops without Reset Terminals

Hiroaki Matsushita,  

[Date]2000/1/12
[Paper #]VLD99-99,CPSY99-108
Scheduling and Placement of Operations Considering Data Communication Time

Masaki Nakano,  Kazuhito Ito,  

[Date]2000/1/12
[Paper #]VLD99-100,CPSY99-109
A Non-Scan DFT Method for RTL Circuits Based on Fixed-Control Testability

Shintaro Nagai,  Hiroki Wada,  Satoshi Ohtake,  Hideo Fujiwara,  

[Date]2000/1/12
[Paper #]VLD99-101,CPSY99-110
Improvement of DES circuit on FPGA-based Parallel Machine "RASH"

Hiroai Asami,  Masahiro IIda,  Katsuto Nakajima,  Hakuro Mori,  

[Date]2000/1/12
[Paper #]VLD99-102,CPSY99-111
Design of FPAccA model 2.0 Chip : Reconfigurable Floating-Point-Unit Array

Yoichi KAWANO,  Hiroyuki OCHI,  Takao TSUDA,  

[Date]2000/1/12
[Paper #]VLD99-103,CPSY99-112
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device

M UNO,  Y. SHIBATA,  H. AMANO,  K. FURUTA,  T. FUJII,  M. MOTOMURA,  

[Date]2000/1/12
[Paper #]VLD99-104,CPSY99-113
PICO^2-The Framework for Education of Pipelined Architecture

Katsunobu Nishimura,  Kazumasa Nukata,  Hideharu Amano,  

[Date]2000/1/12
[Paper #]VLD99-105,CPSY99-114
The KIT COSMOS Processor : Background and Rationale

TOSHINORI SATO,  ITSUJIRO ARITA,  

[Date]2000/1/12
[Paper #]VLD99-106,CPSY99-115
Design of a Cluster Computing System with Distrinbuted Shared Memory Using PCI-Card Implemented withFPGAs

Jun TACHIKAWA,  Yuji KUGE,  Tomohiro OOHAMA,  Koichiro TANAKA,  Toshinori SATO,  Itsujiro ARITA,  

[Date]2000/1/12
[Paper #]VLD99-107,CPSY99-116
[OTHERS]

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[Date]2000/1/12
[Paper #]