Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1999/06/11)

Presentation
表紙

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[Date]1999/6/11
[Paper #]
目次

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[Date]1999/6/11
[Paper #]
[CATALOG]

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[Date]1999/6/11
[Paper #]
Improvements of Decision Algorithm for Presburger Arithmetic in High Level Verification of Logic Circuits

Hiroyuki KAGEYAMA,  Junji KITAMICHI,  Teruo HIGASHINO,  

[Date]1999/6/11
[Paper #]VLD99-30
A Hardware Architecture of Motion Estimator with 8x8 Block Mode for MPEG4 and Its VHDL Model

Kenji SAKAMOTO,  Shogo MURAMATSU,  Hitoshi KIYA,  Akihiko YAMADA,  

[Date]1999/6/11
[Paper #]VLD99-31
LSI Implemetation of Wireless Data System Controller for Medical Cares

Makoto Furuie,  Kenji Matsumura,  Gen Fujita,  Toshihiro Masaki,  Isao Shirakawa,  Hiroshi Inada,  

[Date]1999/6/11
[Paper #]VLD99-32
A Video Coder Architecture based on Discrete Wavelet Transform

Roberto Y. 0MAKI,  Gen FUJITA,  Takao ONOYE,  Isao SHIRAKAWA,  

[Date]1999/6/11
[Paper #]VLD99-33
Circuit and Layout Optimization for Dynamic CMOS Cells with Two Pairs of Power Lines I : Domino CMOS "Quasi-Standard-Cell" Layout

Toshiro Akino,  

[Date]1999/6/11
[Paper #]VLD99-34
Delay Minimization Using a Network Flow Algorithm

Yutaka TAMIYA,  

[Date]1999/6/11
[Paper #]VLD99-35
Clock Scheduling with Consideration of Modification Cost in Semi-Synchrornous Circuit

Tomoyuki Yoda,  Tetsuo Sasaki,  Atsushi Takahashi,  

[Date]1999/6/11
[Paper #]VLD99-36
A Capacitance Extraction Method for Deep-submicron LSI Design

Susumu Kobayashi,  Masato Edahiro,  

[Date]1999/6/11
[Paper #]VLD99-37
A Realization of Multit-Port Gyrator using Current Feedback Amplifiers (CFAs)

Yoshinori Arita,  Hiroyasu Iida,  Masaru Ishida,  Yutaka Fukui,  

[Date]1999/6/11
[Paper #]VLD99-38
A Realizaton of Generalized Impedance Converter (GIC) using Current Feedback Amplifiers (CFAs)

Tomohiko MOTOMURA,  Hiroyasu IIDA,  Masaru ISHIDA,  Yutaka FUKUI,  

[Date]1999/6/11
[Paper #]VLD99-39
A Proposal of quasi-Parallel Divider for Numbers of Arbitary Word Length and its Application for VSI.

Tsugio Nakamura,  Hiroshi Kasahara,  

[Date]1999/6/11
[Paper #]VLD99-40
Structure Method of High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits/3 Bits

Masato Saito,  Mitsuki Hinosugi,  Yoshitaka Tsunekawa,  Mamoru Miura,  

[Date]1999/6/11
[Paper #]VLD99-41
Realizaiton of band stop filter using FPGA.

Wichai Boonkumklao,  Nobuhiro Miki,  

[Date]1999/6/11
[Paper #]VLD99-42
A cell generation method for salicide process

Kazuhisa Okada,  Takayuki Yamanouchi,  Takasi Kambe,  

[Date]1999/6/11
[Paper #]VLD99-43
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[Date]1999/6/11
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