Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1998/12/10)

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[Date]1998/12/10
[Paper #]
目次

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[Date]1998/12/10
[Paper #]
A Hardware System of Self-Reconfigurable 2D-Mesh Multiprocessor

Junya Yamada,  Toru Abe,  Susumu Horiguchi,  

[Date]1998/12/10
[Paper #]VLD98-99,CPSY98-119
Making and Evaluation of the Compiler for WASMII, a Virtual hardware system

A. Takayama,  K. Iwai,  Y. Shibata,  H. Miyazaki,  K. Higure,  X-P. Ling,  H. Amano,  

[Date]1998/12/10
[Paper #]VLD98-100,CPST98-120
A Study on a Reconfigurable Synchronous Dataflow Computer

Hiroshi Sasaki,  Hideaki Tsukioka,  Nobuyoshi Shoji,  Hiroaki Kobayashi,  Tadao Nakamura,  

[Date]1998/12/10
[Paper #]VLD98-101,CPSY98-121
High-Performance Implementation of a Learning Algorithm based on Self-Organization using an FPGA System

Fumio TAKEYA,  Mitinori Iwasaki,  Tsutomu YOSHINAGA,  Masayuki ARAI,  Kanemitsu OOTSU,  Takanobu BABA,  

[Date]1998/12/10
[Paper #]VLD98-102,CPSY98-122
Solving Satisfiability Problems using Reconfigurable Hardware

Takayuki Suyama,  Makoto Yokoo,  Akira Nagoya,  

[Date]1998/12/10
[Paper #]VLD98-103,CPSY98-123
A Fail Safe Circuit for Real-time Controllers Using FPGA

Naoya Chujo,  Tomonori Hashiyama,  Takeshi Furuhashi,  Shigeru Okuma,  

[Date]1998/12/10
[Paper #]VLD98-104,CPSY124
Pattern Recognition LSI's Designed by Direct Data Implementation Technique Using FPGA's

Moritoshi Yasunaga,  Tomochika Takami,  

[Date]1998/12/10
[Paper #]VLD98-105,CPSY98-125
A Reciprocal Number Calculation Circuit Design for FPGA

W Ogata,  H Kasahara,  

[Date]1998/12/10
[Paper #]VLD98-106,CPSY98-126
Design of Digital Signal Processing FPGA Architecture Using New Redundant Number Representation

Yoshiki SAWADA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]1998/12/10
[Paper #]VLD98-107,CPSY98-127
A Realization of Devices Simulation Engine

Eisaku TOMITA,  Toshio YAMAMOTO,  Yukihiro IGUCHI,  

[Date]1998/12/10
[Paper #]VLD98-108,CPSY98-128
A Realization of Cycle-based Simulation Engine

Atsumu ISENO,  Yukihiro IGUCHI,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]1998/12/10
[Paper #]VLD98-109,CPSY98-129
An Efficient Disjunctive Decomposition Algorithm and Its Application to Logic Synthesis

Yusuke Matsunaga,  

[Date]1998/12/10
[Paper #]VLD98-110,CPSY98-130
A Method for Synthesizing LUT Networks Integrating Various Decomposition Methods

Shigeru Yamashita,  Hiroshi Sawada,  Akira Nagoya,  

[Date]1998/12/10
[Paper #]VLD98-111,CPSY98-131
New Algebraic Expressions for Combinational and Sequential Circuits on FPGAs

Koichi Yasuoka,  

[Date]1998/12/10
[Paper #]VLD98-112,CPSY98-132
A Synthesis Method for Asynchronous Logic Circuits on Array of LUTs

Ryusuke Konishi,  Kiyoshi Oguri,  Hideyuki Ito,  Kouichi Nagami,  

[Date]1998/12/10
[Paper #]VLD98-113,CPSY98-133
New Array-Based Mapping Algorithm of Logic Funcations into Plastic Cell Architecure

Ryuji Kan,  Tomonori Izumi,  Yukihiro Nakamura,  

[Date]1998/12/10
[Paper #]VLD98-114,CPSY98-134
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Macro-Blocks

Daisuke INOUE,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]1998/12/10
[Paper #]VLD98-115,CPSY98-135
Maxflow based Method for Enumerating Mincut Edges of Graph Modelled Logic Circuit

Kengo Azegami,  Atsushi Takahashi,  Yoji Kajitani,  

[Date]1998/12/10
[Paper #]VLD98-116,CPSY98-136
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