Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1998/09/22)

Presentation
表紙

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[Date]1998/9/22
[Paper #]
目次

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[Date]1998/9/22
[Paper #]
A High-Performance/Low-Energy Cache Architecture with Way-Prediction Technique

Koji Inoue,  Tohru Ishihara,  Kazuaki Murakami,  

[Date]1998/9/22
[Paper #]VLD98-44,ICD98-147,FTS98-71
Evaluation of Standard Cell Libraries for VDEC

Akihiko HYOUDOU,  Tohru ISHIHARA,  Khaled JAMALEDDINE,  Hiroto YASUURA,  

[Date]1998/9/22
[Paper #]VLD98-45,ICD98-148,FTS98-72
C++ Simulator "ClassMate" for pre-verification on SOC

Hidefumi Kurokawa,  

[Date]1998/9/22
[Paper #]VLD98-46,ICD98-149,FTS98-73
Estimation of Peak Current through CMOS VLSI Circuit Supply Lines

Toshio Murayama,  Kimihiro Ogawa,  Haruhiko Yamaguchi,  

[Date]1998/9/22
[Paper #]VLD98-47,ICD98-150,FTS98-74
VCO Jitter Simulation and Its Comparison With Measurement

Masayuki Takahashi,  Kimihiro Ogawa,  Kenneth S. Kundert,  

[Date]1998/9/22
[Paper #]VLD98-48,ICD98-151,FTS98-75
An effective routing method besed on FPGA routing resource architecture

Takahiro Murooka,  Atsushi Takahara,  Toshiaki Miyazaki,  

[Date]1998/9/22
[Paper #]VLD98-49,ICD98-152,FTS98-76
A Clock-Routing Method for Semi-Synchronous Circuits

Shinya Nishikawa,  Atsushi Takahashi,  Yoji Kajitani,  

[Date]1998/9/22
[Paper #]VLD98-50,ICD98-153,FTS98-77
Design of Completion Prediction Adder with Shift Operation and Its Application to Microprocessor

Ruotong Zheng,  Kunihiro Asada,  

[Date]1998/9/22
[Paper #]VLD98-51,ICD98-154,FTS98-78
VLSI Implementation of a Recursive Maximum Likelihood Decoder dedicated to High-Speed Satellite Communication

Daisuke TAKI,  Morgan Hirosuke Miki,  Gen FUJITA,  Takao ONOYE,  Isao SHIRAKAWA,  Toru FUJIWARA,  Tadao KASAMI,  

[Date]1998/9/22
[Paper #]VLD98-52,ICD98-155,FTS98-79
Low Power Consumption LSI Design with Soft Core IP : An Application of Power-Conscious CMOS Cell Library

Kiyohide HORI,  Yutaka MURATA,  Kazuo TAKI,  

[Date]1998/9/22
[Paper #]VLD98-53,ICD98-156,FTS98-80
Mega-gate ASIC implement design

Chiaki KOGA,  Hideki SAKAMOTO,  Masayuki TSUDA,  Akira OHAMA,  Noritoshi YAMAKAWA,  Makoto UCHIBA,  Masataka OHSATO,  

[Date]1998/9/22
[Paper #]VLD98-54,ICD98-157,FTS98-81
Development and Design of mega gate level LSI by using VHDL

Hideo Fujita,  Shunichi Tonai,  Kouichi Kawarabata,  Gyou Baba,  Mituharu Wakayosi,  Akikazu Maehara,  Kenichi Okabe,  

[Date]1998/9/22
[Paper #]VLD98-55,ICD98-158,FTS98-82
2.7ns 0.25μmCMOS 54x54b Multiplier

Yasuhiko Hagihara,  Atsushi Yoshikawa,  Shigeto Inui,  Satoshi Nakazato,  Manabu Kurohashi,  Shuzo Murai,  Kazuyuki Suganami,  Shigehito Tameda,  Mutsumi Aoki,  Masakazu Yamashina,  

[Date]1998/9/22
[Paper #]VLD98-56,ICD98-159,FTS98-83
DECOMPOS : An Integrated System for Functional Decomposition

Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]1998/9/22
[Paper #]VLD98-57,ICD98-160,FTS98-84
On a Method to Accelerate Functional Decompositions

Tsutomu SASAO,  

[Date]1998/9/22
[Paper #]VLD98-58,ICD98-161,FTS98-85
A New System Specification Description Language for the Hardware/Software Co-Design System

Shoichi KATAOKA,  Yutaka TAMAGAKI,  Toshiaki KOWATARI,  

[Date]1998/9/22
[Paper #]VLD98-59,ICD98-162,FTS98-86
On Accelerating Pattern Matching for Technology Mapping

Yusuke Matsunaga,  

[Date]1998/9/22
[Paper #]VLD98-60,ICD98-163,FTS98-87
A Study of Pass-Transistor Logic Synthesis

Takayuki Yamanouchi,  Hiroshi Honjo,  Tetsuya Fujimoto,  

[Date]1998/9/22
[Paper #]VLD98-61,ICD98-164,FTS98-88
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