Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1998/06/26)

Presentation
表紙

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[Date]1998/6/26
[Paper #]
目次

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[Date]1998/6/26
[Paper #]
A Realization of a Nonlinear Transconductor with (2n-1) Different Negative Conductance Segments and Its Application to Chaos Circuits

Kazuya Kotaka,  Takahiro Inoue,  Akio Tsuneda,  Tetsuo Arakawa,  

[Date]1998/6/26
[Paper #]CAS98-15,VLD98-15,DSP98-44
Properties of Chaotic Sequences Generated by Finite-Bit Operations

Kuniaki Ishida,  Akio Tsuneda,  Takahiro Inoue,  

[Date]1998/6/26
[Paper #]CAS98-16,VLD98-16,DSP98-45
A Note on LSI Design with Flexibility of Lattice Filters

Nobuhiro Miki,  Wichai Boonkumklao,  Tomoaki Shirakawa,  Yoshihiko Ogawa,  

[Date]1998/6/26
[Paper #]CAS98-17,VLD98-17,DSP98-46
A proposition of the binary pattern recognition algorithm and its digital hardware implementation

Yusuke Tokunaga,  Takahiro Inoue,  

[Date]1998/6/26
[Paper #]CAS98-18,VLD98-18,DSP98-47
Redundant Binary Adder Representing 1 Digit by 3 Bits and Its Application to Multiplier

Mitsuki Hinosugi,  Masato Saito,  Katsumi Abukawa,  Yoshitaka Tsunekawa,  Mamoru Miura,  

[Date]1998/6/26
[Paper #]CAS98-19,VLD98-19,DSP98-48
Placement Optimization by Simulated Phase Transition

Masahiko Toyonaga,  Toshiro Akino,  

[Date]1998/6/26
[Paper #]CAS98-20,VLD98-20,DSP98-49
Iterative Generation of Steiner Trees by Flip for Optimum Interconnection Layout

Yasuhiro Takashima,  Tsuyoshi Kurasawa,  Shigetoshi Nakatake,  Yoji Kajitani,  

[Date]1998/6/26
[Paper #]CAS98-21,VLD98-21,DSP98-50
Stochastic Approach to an Optimal Interconnection Layout for Planar Routing

Yukiko Kubo,  Yasuhiro Takashima,  Shigetoshi Nakatake,  Yoji Kajitani,  

[Date]1998/6/26
[Paper #]CAS98-22,VLD98-22,DSP98-51
Evolutionary Generation of Arithmetic Circuit structures

Naofumi HOMMA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]1998/6/26
[Paper #]CAS98-23,VLD98-23,DSP98-52
Radix-4 Dividers without Using Quotient Digit Selection Tables

Osamu MIURA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]1998/6/26
[Paper #]CAS98-24,VLD98-24,DSP98-53
Motion Estimation Based on Software Pipelining with Conditional Branches

Katsumi TAKAYAMA,  Takeshi UCHIDA,  Hitoshi KIYA,  Akihiko YAMADA,  

[Date]1998/6/26
[Paper #]CAS98-25,VLD98-25,DSP98-54
Barrier Synchronizer LSI which can Resolve Pseudo Dependency caused by Partial Order Barrier Groups

Tatsuo TSUCHIE,  Tetsuo HIRONAKA,  

[Date]1998/6/26
[Paper #]CAS98-26,VLD98-26,DSP98-55
A Reconfigurable Digital Signal Processor

B.K Tan,  R Yoshimura,  M Ichihashi,  T Ogawa,  K Taniguchi,  

[Date]1998/6/26
[Paper #]CAS98-27,VLD98-27,DSP98-56
Statistical Performance-Driven Module Binding in High-Level Synthesis

Hiroyuki TOMIYAMA,  Akihiko INOUE,  Hiroto YASUURA,  

[Date]1998/6/26
[Paper #]CAS98-28,VLD98-28,DSP98-57
System-Level Energy Optimization for Embedded Systems with a Variable Datapath Width Processor

Akihiko INOUE,  Hiroyuki TOMIYAMA,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]1998/6/26
[Paper #]CAS98-29,VLD98-29,DSP98-58
[OTHERS]

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[Date]1998/6/26
[Paper #]