Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1997/10/29)

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[Date]1997/10/29
[Paper #]
目次

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[Date]1997/10/29
[Paper #]
A VLSI Processor Architecture for Fault-Tolerant Software and Systems

Satoshi OGAWA,  

[Date]1997/10/29
[Paper #]VLD97-79
Full-Scan Testing on Boards with The Boundary-Scan Technique

Yasunori Sameshima,  Tomoo Fukazawa,  

[Date]1997/10/29
[Paper #]VLD97-80
A Non-Scan DFT Method for RTL Data Paths To Provide Complete Fault Efficiency

Hiroki WADA,  Toshimitsu MASUZAWA,  Kewal K. Saluja,  Hideo FUJIWARA,  

[Date]1997/10/29
[Paper #]VLD97-81
Masking Double Faults in Combinational Circuits Using Retry Scheme and Hamming Code

Takeo YOSHIDA,  

[Date]1997/10/29
[Paper #]VLD97-82
Path Selection Based on Real Delay Estimation for Path Delay Fault Testing

Seiichiro Tani,  Mitsuo Teramoto,  Tomoo Fukazawa,  Kazuyoshi Matsuhiro,  

[Date]1997/10/29
[Paper #]VLD97-83
Minimum Tests for Stuck-at Faults of the Adders

Seiji Kajihara,  Tsutomu Sasao,  

[Date]1997/10/29
[Paper #]VLD97-84
Implementation of Test Pattern Generation and Control Circuits in Memory Burn-In Testers by using FPGAs

Yukihiro IGUCHI,  Tomoomi KISHINO,  Haruo YOKOYAMA,  

[Date]1997/10/29
[Paper #]VLD97-85
A design methodology for application specific FPGAs

Atsushi Takahara,  Toshiaki Miyazaki,  Masaru Katayama,  Takahiro Murooka,  Akihiro Tsutsui,  Kazuhiro Hayashi,  Takaki Ichimori,  Kennosuke Fukami,  

[Date]1997/10/29
[Paper #]VLD97-86
An Efficient Formal Verification Method for the Circuit Specification with Several Modules

Takashi TAKENAKA,  Junji KITAMICHI,  Seishi NISHIKAWA,  

[Date]1997/10/29
[Paper #]VLD97-87
Efficient Manipulation on Implicit Representation of Binary Decision Diagrams

Hitoshi Yamauchi,  Hiromitsu Takahashi,  

[Date]1997/10/29
[Paper #]VLD97-88
Instruction Set Processor Synthesis Method based on Behavioral Semantics Description

Makiko Itoh,  Yoshinori Takeuchi,  Masaharu Imai,  Akichika Shiomi,  

[Date]1997/10/29
[Paper #]VLD97-89
A Method of Retargetable Compilation for Embedded Systems

Masayuki YAMAGUCHI,  Nagisa ISHIURA,  Takashi KAMBE,  

[Date]1997/10/29
[Paper #]VLD97-90
A High-Level Synthesis System for Embeded System

Tetsusaburo YAMAMOTO,  Nagisa ISHIURA,  Masayuki YAMAGUCHI,  Yasushi HATTORI,  

[Date]1997/10/29
[Paper #]VLD97-91
A Functional Unit Configuration Optimizing Method for VLIW Processor Design Automation

Norimasa Ohtsuki,  Yoshinori Takeuchi,  Masaharu Imai,  Kiyoharu Hamaguchi,  Toshinobu Kashiwabara,  Nobuyuki Hikichi,  

[Date]1997/10/29
[Paper #]VLD97-92
Module Selection Using Manufacturing Information

Hiroyuki Tomiyama,  Hiroto Yasuura,  

[Date]1997/10/29
[Paper #]VLD97-93
A Module Generator for Embedded DRAM Macros

Hideki Takeuchi,  Tomoaki Yabe,  Shinji Miyano,  Takehiko Hojyo,  Masaaki Tazawa,  Motohiro Enkaku,  Masaaki Yamada,  Masami Murakata,  

[Date]1997/10/29
[Paper #]VLD97-94
A DRAM Based Functional Memory for Addition

Masaki Kondo,  Yukifumi Kobayashi,  Kazutoshi Kobayashi,  Keikichi Tamaru,  

[Date]1997/10/29
[Paper #]VLD97-95
A Hierarchical Floorplanning Method using Genetic Algorithm

Chiaki SUGIMOTO,  Takashi SHIMAMOTO,  Akio SAKAMOTO,  Hiroyuki SUZUKI,  Hiroomi ANZAI,  

[Date]1997/10/29
[Paper #]VLD97-96
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