Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1996/09/27)

Presentation
表紙

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[Date]1996/9/27
[Paper #]
目次

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[Date]1996/9/27
[Paper #]
Numerical Simulation of Drain Lag in HJFETs with a Buried p-Buffer Layer

Masanobu Nogome,  Kazuaki Kunihiro,  Yasuo Ohno,  

[Date]1996/9/27
[Paper #]VLD96-41,ED96-87,SDM96-97
Sensitivity Analysis of Device Characteristic in CMOS using TCAD

Kimiko Ichikawa,  Katsumi Tsuneno,  Hisako Sato,  Hiroo Masuda,  

[Date]1996/9/27
[Paper #]VLD96-42,ED96-88,SDM96-98
Design parameter dependence and optimization of drain characteristics of DTMOS

S. Komatsu,  R. Ikeno,  H. Ito,  K. Asada,  

[Date]1996/9/27
[Paper #]VLD96-43,ED96-89,SDM96-99
An Analysis of the Electrical Characteristics of a-Si:H TFT's Including Contact Current-Voltage Characteristics

K. Sonoda,  K. Eikyu,  K. Ishikawa,  T. Nishimura,  T. Yamaguchi,  N. Nakagawa,  

[Date]1996/9/27
[Paper #]VLD96-44,ED96-90,SDM96-100
Complementary Charge Pump Voltage Booster

Kazukiyo TAKAHASHI,  Shouyu WANG,  Mitsuru MIZUNUMA,  

[Date]1996/9/27
[Paper #]VLD96-45,ED96-91,SDM96-101
Simulator for Cosmic Ray Neutron Induced Soft Errors and Its Applications

Yoshiharu Tosaka,  Shigeo Satoh,  Toru Itakura,  

[Date]1996/9/27
[Paper #]VLD96-46,ED96-92,SDM96-102
Physical model for breakdown simulation

K. Matsuzawa,  Y. Oowaki,  N. Aoki,  N. Shigyo,  

[Date]1996/9/27
[Paper #]VLD96-47,ED96-93,SDM96-103
Semi-two dimensional dopant profile extraction of deep submicron MOSFETs by inverse modeling

K. Kai,  H. Hayashi,  K. Fukuda,  K. Nishi,  

[Date]1996/9/27
[Paper #]VLD96-48,ED96-94,SDM96-104
New Capacitance Formulation and Delay Optimum Aspect Ratio for VLSI Interconnections

T. Mido,  K. Asada,  

[Date]1996/9/27
[Paper #]VLD96-49,ED96-95,SDM96-105
Evaluation of Circuit Partitioning for the Simulation of Memory Circuits

Mikako Miyama,  Takashi Sato,  Saburo Hojo,  Kojiro Niho,  

[Date]1996/9/27
[Paper #]VLD96-50,ED96-96,SDM96-106
[OTHERS]

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[Date]1996/9/27
[Paper #]