Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1996/03/08)

Presentation
表紙

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[Date]1996/3/8
[Paper #]
目次

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[Date]1996/3/8
[Paper #]
NETWORK RECONFIGURATION ON WSI WITH LIMITED NUMBER OF TRACKS

Takahiro Hirota,  Mineo Kaneko,  

[Date]1996/3/8
[Paper #]VLD95-143,ICD95-243
A synthesis method of fault-tolerant system for a singular operational module fault

Tsuyoshi Yaguchi,  Mineo Kaneko,  

[Date]1996/3/8
[Paper #]VLD95-144,ICD95-244
Design Automation for Integrated Continuous-Time Filters Considering Integrator Nonidealities

Kazuyuki WADA,  Shigetaka TAKAGI,  Zdzislaw Czarnul,  Nobuo FUJII,  

[Date]1996/3/8
[Paper #]VLD95-145,ICD95-245
A Design Method of Fundamental Logic Elements Using Neuron MOS Transistors

Kenjirou IKE,  Kei HIROSE,  Hiroto YASUURA,  

[Date]1996/3/8
[Paper #]VLD95-146,ICD95-246
An Evaluation of Parallel Multipliers using Neuron MOS Transistors

Kei HIROSE,  Hiroto YASUURA,  

[Date]1996/3/8
[Paper #]VLD95-147,ICD95-247
A Module Generator for a Multiplier Realizing Delay-Power-Area Trade off

Kow San Fam,  Keikichi Tamaru,  

[Date]1996/3/8
[Paper #]VLD95-148,ICD95-248
Logic/Circuit Mixed-Mode Simulation incorporating Power Supply Voltage Fluctuation

Mikako Miyama,  Goichi Yokomizo,  Masato Iwabuchi,  Masami Kinoshita,  

[Date]1996/3/8
[Paper #]VLD95-149,ICD95-249
Dual Threshold Delay Model for Nonlinear Device Characterization

Nobufusa Iwanishi,  Yasuhiro Tomita,  Ryuichi Yamaguchi,  Hisakazu Edamatsu,  

[Date]1996/3/8
[Paper #]VLD95-150,ICD95-250
Technology Mapping for FPGAs based on Subcircuit Shrinking

Yoshiki Yasutomi,  Toshimasa Watanabe,  

[Date]1996/3/8
[Paper #]VLD95-151,ICD95-251
CMOS Logic Circuit Synthesis with Iterative Cell Optimization

Jialin Tian,  Masachika Sasaki,  Mineo Kaneko,  

[Date]1996/3/8
[Paper #]VLD95-152,ICD95-252
Fanout-tree Restructuring Algorithm for Post-placement Timing Optimization

T. Aoki,  M. Murakata,  T. Mituhashi,  N. Goto,  

[Date]1996/3/8
[Paper #]VLD95-153,ICD95-253
A New Hierarchical Algorithm for Transistor Placement in CMOS Macro Cell Design

Toshiyuki Sadakane,  Hiroomi Nakao,  Masayuki Terai,  

[Date]1996/3/8
[Paper #]VLD95-154,ICD95-254
A Layout Optimization Algorithm for Leaf Cells with Bent Gates

Noriko Shinomiya,  Masahiro Fukui,  Syunji Saika,  Toshiro Akino,  

[Date]1996/3/8
[Paper #]VLD95-155,ICD95-255
A New 2-Dimensional Transistor Placement in Leaf Cell Layout Synthesis

Shunji Saika,  Masahiro Fukui,  Noriko Shinomiya,  Toshiro Akino,  

[Date]1996/3/8
[Paper #]VLD95-156,ICD95-256
An Extension of Pitchmatching Algorithms to Layouts with Multiple Grid Constraints

Hiroshi Miyashita,  

[Date]1996/3/8
[Paper #]VLD95-157,ICD95-257
A Top-Down Router for Delay Minimization

Katsuya YAMAMOTO,  Takashi HAGA,  Shuji TSUKIYAMA,  

[Date]1996/3/8
[Paper #]VLD95-158,ICD95-258
[OTHERS]

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[Date]1996/3/8
[Paper #]