Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1996/03/07)

Presentation
表紙

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[Date]1996/3/7
[Paper #]
目次

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[Date]1996/3/7
[Paper #]
DFT of Bridging Faults in Logic Circuits with Current Testing

Masaki Hashizume,  Takeomi Tamesada,  Takeshi Yano,  

[Date]1996/3/7
[Paper #]VLD95-129,ICD95-229
RTL Partitioning Method for Design For Testability

Toshinori Hosokawa,  Kenichi Kawaguchi,  Mitsuyasu Ohta,  Sadami Takeoka,  Michiaki Muraoka,  

[Date]1996/3/7
[Paper #]VLD95-130,ICD95-230
Full Top Down Design for Testability Using Multi-Level Partial Scan Design

Akira Motohara,  Sadami Takeoka,  Toshinori Hosokawa,  Mitsuyasu Ohta,  Yuji Takai,  Michihiro Matsumoto,  Michiaki Muraoka,  

[Date]1996/3/7
[Paper #]VLD95-131,ICD95-231
A Tool for Measuring Quality of Test Pattern for LSIs' Functional Design

Takashi Aoki,  Tomoji Toriyama,  Keiji Ishikawa,  Kennosuke Fukami,  

[Date]1996/3/7
[Paper #]VLD95-132,ICD95-232
A Time-Constrained Scheduling Algorithm for CDFG with Conditional Branches

Hiroaki ISHIWATA,  Nozomu TOGAWA,  Masao SATO,  Tatsuo OHTSUKI,  

[Date]1996/3/7
[Paper #]VLD95-133,IC95-233
A Pipelined Scheduling Algorithm for DFG with Inter Iteration Data Dependencies

Koichi NISHIDA,  Nozomu TOGAWA,  Masao SATO,  Tatsuo OHTSUKI,  

[Date]1996/3/7
[Paper #]VLD95-134,ICD95-234
An Algorithm for Combined Module Selection and Resource Sharing in Pipelined Data-Path Synthesis

Shin-ya Furusawa,  Vasily Moshnyaga,  Hidetosi Onodera,  Keikichi Tamaru,  

[Date]1996/3/7
[Paper #]VLD95-135,ICD95-235
Prospect of Sub-Quarter Micron LSI Design

Masakazu Yamashina,  

[Date]1996/3/7
[Paper #]VLD95-136,ICD95-236
Micro-Operation Level Optimal Datapath Synthesis for Application Specific Instruction-Set Processor

Kyung-Sik Jang,  Hiroaki Kunieda,  

[Date]1996/3/7
[Paper #]VLD95-137,ICD95-237
High-Level Synthesis for Array Architecture Digital Signal Processing Systems

Tadashi Iwata,  Kazuhito Ito,  Hiroaki Kunieda,  

[Date]1996/3/7
[Paper #]VLD95-138,ICD95-238
Architecture design of bit-serial digital signal processing parallel processor

Takenobu Shimizugashira,  Masahiro Saitoh,  Akihisa Ohta,  Hiroaki Kunieda,  

[Date]1996/3/7
[Paper #]VLD95-139,ICD95-239
ASIC Design Methodology for MSPA Architecture and its application to Data-serial Matrix Multiplier

Dongju Li,  Kazuhito Ito,  Hiroaki Kunieda,  

[Date]1996/3/7
[Paper #]VLD95-140,ICD95-240
High-speed Low-power Bipolar Standard Cell Design Methodology or Multi-Gbit/s Signal Processing

Keiichi KOIKE,  Kenji KAWAI,  Akira ONOZAWA,  Yuichiro TAKEI,  Yoshiji KOBAYASHI,  Haruhiko ICHINO,  

[Date]1996/3/7
[Paper #]VLD95-141,ICD95-241
Can Design and CAD Technology meet the challenge in Deep Sub-micron Era ?

M. Yamashina,  E. Masuda,  H. Edamatsu,  T. Hasegawa,  Y. Ogawa,  T. Watanabe,  H. Onodera,  T. Mitsuhashi,  

[Date]1996/3/7
[Paper #]VLD95-142,ICD95-242
[OTHERS]

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[Date]1996/3/7
[Paper #]