Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1995/12/14)

Presentation
表紙

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[Date]1995/12/14
[Paper #]
目次

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[Date]1995/12/14
[Paper #]
A Probability-based Approach for Data Path Allocation

Miki Yoshida,  Yusuke Hirakawa,  Katsumi Harashima,  Kunio Fukunaga,  

[Date]1995/12/14
[Paper #]VLD95-101
A Scheduling Method for Pipelined Datapaths Considering Register-to-Register Data Transfers

Katsumi HARASHIMA,  Hironori KOMI,  Kunio FUKUNAGA,  

[Date]1995/12/14
[Paper #]VLD95-102
Exact-Probability Oriented Scheduling of Data-Flow Graph

Akihiro Matsuura,  Ryo Nomura,  Akira Nagoya,  

[Date]1995/12/14
[Paper #]VLD95-103
A Global Code Scheduling Technique with Register Allocation for Fine Grain Parallel Processors

Akihiko Inoue,  Hiroki Akaboshi,  Hiroyuki Tomiyama,  Kazutoshi Wakabayashi,  Hiroto Yasuura,  

[Date]1995/12/14
[Paper #]VLD95-104
A Thread Generating Method with Genetic Algorithms

Kiyokazu Katayama,  Shuichi Ichikawa,  Toshio Shimada,  

[Date]1995/12/14
[Paper #]VLD95-105
Dynamic Load Balancing Method in Consideration of History for the Distributed Systems

Hiroyuki Sugiura,  Shuichi Ichikawa,  Toshio Shimada,  

[Date]1995/12/14
[Paper #]VLD95-106
NSL: Parallel Numerical Simulation Language : Implementation Using Distributed Array Library and Performance Evaluation

Takamitsu Kawai,  Shuichi Ichikawa,  Toshio Shimada,  

[Date]1995/12/14
[Paper #]VLD95-107
Slicing Algorithm for Delta-Delay VHDL Descriptions

Shigeru Ichinose,  Masaya Nomura,  Mizuho Iwaihara,  Hiroto Yasuura,  

[Date]1995/12/14
[Paper #]VLD95-108
Automatic Generation of RTL Model in Standard HDL from Gate/Transistor Circuits for High-Speed Simulation

Tetsuroo Horrmura,  Takao Shinsha,  Makoto Obata,  Satoshi Kojima,  

[Date]1995/12/14
[Paper #]VLD95-109
Switch-level simulation on communicating EWS's

Atsushi Kageshima,  Kimiyoshi Usami,  Jyun-ichi Tsujimoto,  

[Date]1995/12/14
[Paper #]VLD95-110
An Iterative Improvement Method for Evaluating the Maximum Number of Simultaneous Switching Gates for Combinational Circuits

Kai Zhang,  Tsuyoshi Shinogi,  Terumine Hayashi,  Hidehiko Kita,  

[Date]1995/12/14
[Paper #]VLD95-111
Architectural-level Power Estimation for CMOS RISC Processors

Toshinori SATO,  Yukio OOTAGURO,  Masato NAGAMATSU,  Haruyuki TAGO,  

[Date]1995/12/14
[Paper #]VLD95-112
Board-level simulation with R4400 model

Hiroki Narita,  Toshio Sando,  Takahiro Kimura,  Takumi Hasegawa,  Etsuo Takahashi,  

[Date]1995/12/14
[Paper #]VLD95-113
An Architecture Evaluation Method based on the Structure of Datapath Resources

Masayuki YAMAGUCHI,  Akihisa YAMADA,  Toshihiro NAKAOKA,  Takashi KAMBE,  

[Date]1995/12/14
[Paper #]VLD95-114
[OTHERS]

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[Date]1995/12/14
[Paper #]