Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1995/10/19)

Presentation
表紙

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[Date]1995/10/19
[Paper #]
目次

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[Date]1995/10/19
[Paper #]
A Fault Simulation method for crosstalk faults in synchronous sequential circuits

Yasutaka Idomoto,  Noriyoshi Itazaki,  Kozo Kinoshita,  

[Date]1995/10/19
[Paper #]VLD95-78,FTS95-40
On Improvement of an ATPG based on Real-valued Logic Simulation

Tsuyoshi Shinogi,  Tomoyuki Uchida,  Hidehiko Kita,  Terumine Hayashi,  

[Date]1995/10/19
[Paper #]VLD95-79,FTS95-41
A Study for Fault Diagnosis in Sequential Circuits using Sensitizing Sequence Pairs

Nobuhiro Yanagida,  Hiroshi Takahashi,  Yuzo Takamatsu,  

[Date]1995/10/19
[Paper #]VLD95-80,FTS95-42
On Testing of Josephson Logic Circuits

Teruhiko Yamada,  Tsuyoshi Sasaki,  

[Date]1995/10/19
[Paper #]VLD95-81,FTS95-43
A Fault Location System for Complex LSIs

Masaki Gotoh,  Hiroshi Odani,  Fumihiko Shirotori,  

[Date]1995/10/19
[Paper #]VLD95-82,FTS95-44
Logic Verification for Super Scalar MPU

Takeshi Ibusuki,  Hideki Adachi,  

[Date]1995/10/19
[Paper #]VLD95-83,FTS95-45
Efficient Construction of Binary Moment Diagrams for Verifying Arithmetic Circuits

Kiyoharu HAMAGUCHI,  Akihito MORITA,  Shuzo YAJIMA,  

[Date]1995/10/19
[Paper #]VLD95-84,FTS95-46
On Functional Implication and Its Application to Equivalence Checking of Combinational Circuits

Yusuke Matsunaga,  

[Date]1995/10/19
[Paper #]VLD95-85,FTS95-47
A Timing Driven Placement Algorithm in Arithmetic Logic Circuits

Takeshi Nakamura,  Akimichi Kojima,  Katsuya Furuki,  

[Date]1995/10/19
[Paper #]VLD95-86,FTS95-48
AC YIELD PREDICTION

Kanji Hirabayashi,  

[Date]1995/10/19
[Paper #]VLD95-87,FTS95-49
Power-Optimal Transistor Sizing Incorporating Short-Circuit Effect

Naohito Kojima,  Masaaki Yamada,  Takashi Mitsuhashi,  Nobuyuki Goto,  

[Date]1995/10/19
[Paper #]VLD95-88,FTS95-50
[OTHERS]

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[Date]1995/10/19
[Paper #]