Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1994/03/10)

Presentation
表紙

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[Date]1994/3/10
[Paper #]
目次

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[Date]1994/3/10
[Paper #]
Design method for the 32bit Microprocessor GMICRO/400

Yukari Takata,  Yuichi Saito,  Toyohiko Yoshida,  Tatsuya Ueda,  Masahito Matsuo,  Hiroyuki Kondo,  

[Date]1994/3/10
[Paper #]VLD93-98,ICD93-193
Topdown design of a Monte Carlo device simulation processor with hardware description language

Norihiko Kuroishi,  Sergey Pidin,  Kazunari Tanaka,  Reiji Aibara,  Tetsuro Kawata,  Nobuaki Miyakawa,  Mitsumasa Koyanagi,  

[Date]1994/3/10
[Paper #]VLD93-99,ICD93-194
Design of a Robot Vision VLSI Processor for Obstacle Avoidance of an Intelligent Robot

Yuichi Araumi,  Masanori Hariyama,  Michitaka Kameyama,  

[Date]1994/3/10
[Paper #]VLD93-100,ICD93-195
Design of the digital filter utilizing an Extended Verilog-HDL

Yoshihito Kondo,  Takao Yamazaki,  Seiichiro Iwase,  

[Date]1994/3/10
[Paper #]VLD93-101,ICD93-196
High-level synthesis of VLSI processors for intelligent integrated systems and its evaluation

Yasuaki Sawano,  Bumchul Kim,  Michitaka Kameyama,  

[Date]1994/3/10
[Paper #]VLD93-102,ICD93-197
New Features of High Level Synthesis System:PARTHENON

Takayuki Suyama,  Akira Nagoya,  Kiyoshi Oguri,  Mitsuteru Yukishita,  Hiroshi Sekigawa,  

[Date]1994/3/10
[Paper #]VLD93-103,ICD93-198
A method of logic optimization based on implication procedures

Seiji Kajihara,  Katsuyoshi Watanabe,  Kozo Kinoshita,  

[Date]1994/3/10
[Paper #]VLD93-104,ICD93-199
Fast Weak-Division Method for Implicit Cube Sets Using Zero- Suppressed BDDs

Shin-ichi Minato,  

[Date]1994/3/10
[Paper #]VLD93-105,ICD93-200
30 Years of Design Automation

Akihiko Yamada,  

[Date]1994/3/10
[Paper #]VLD93-106,ICD93-201
A State Traversal Method Based on a State Covariance Matrix Calculation

Akira Motohara,  Toshinori Hosokawa,  Michiaki Muraoka,  Hidetsugu Maekawa,  Kazuhiro Kayashima,  Yasuharu Shimeki,  Seiichi Shin,  

[Date]1994/3/10
[Paper #]VLD93-107,ICD93-202
A General Testable Design of Logic Circuits under Highly Observable Condition

Xiaoqing Wen,  Hideo Tamamoto,  Kozo Kinoshita,  

[Date]1994/3/10
[Paper #]VLD93-108,ICD93-203
A reduced scan shift method for sequential circuit testing using state transitions

Yoshinobu Higami,  Seiji Kajihara,  Kozo Kinoshita,  

[Date]1994/3/10
[Paper #]VLD93-109,ICD93-204
Design for Testability in a Graphical Functional Design System Environment

Akira Motohara,  Yuji Takai,  Toshinori Hosokawa,  Michihiro Matsumoto,  Michiaki Muraoka,  

[Date]1994/3/10
[Paper #]VLD93-110,ICD93-205
[OTHERS]

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[Date]1994/3/10
[Paper #]