Engineering Sciences/NOLTA-Signal Processing(Date:2012/10/11)

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[Date]2012/10/11
[Paper #]
目次

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[Date]2012/10/11
[Paper #]
Human Behavior Detection Using Direction Change Invariant Features of Cubic Higher Order Local Auto Correlation

Takeyuki ISHII,  Hitomi MURAKAMI,  Atsushi KOIKE,  

[Date]2012/10/11
[Paper #]VLD2012-40,SIP2012-62,ICD2012-57,IE2012-64
Avoiding Error Magnification in Weighted Median Cut Quantization in Decoding Process : High Quality Data Compression of Sparse Histogram Images

Toru IKARASHI,  Masahiro IWAHASHI,  Hitoshi KIYA,  

[Date]2012/10/11
[Paper #]VLD2012-41,SIP2012-63,ICD2012-58,IE2012-65
A Design of Hilbert Transformers using an L_1 error criterion

Ikuya MURAKAMI,  Naoyuki AIKAWA,  

[Date]2012/10/11
[Paper #]VLD2012-42,SIP2012-64,ICD2012-59,IE2012-661
A 16-gray-scale image recognition on a dynamically reconfigurable vision architecture

Yuki KAMIKUBO,  Minoru WATANABE,  Shoji KAWAHITO,  

[Date]2012/10/11
[Paper #]VLD2012-43,SIP2012-65,ICD2012-60,IE2012-67
Learning of shade for beginners based on interactive pencil-drawing learning support system using tablet PC

Akihiro SAWADA,  Masashi KAMEDA,  

[Date]2012/10/11
[Paper #]VLD2012-44,SIP2012-66,ICD2012-61,IE2012-68
Computing Technologies for Human-Centered Real-World Intelligent Systems

Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2012/10/11
[Paper #]VLD2012-45,SIP2012-67,ICD2012-62,IE2012-69
Power consumption analysis of a mono instruction set computer architecture

Hiroyuki ITO,  Minoru WATANABE,  

[Date]2012/10/11
[Paper #]VLD2012-46,SIP2012-68,ICD2012-63,IE2012-70
Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size

Yoshichika FUJIOKA,  Michitaka KAMEYAMA,  

[Date]2012/10/11
[Paper #]VLD2012-47,SIP2012-69,ICD2012-64,IE2012-71
Design of Stochastic Flash A/D Converter using a non-linearity calibration technique

Shinya YANO,  Hyunju HAM,  Toshimasa MATSUOKA,  Jun WANG,  Ikkyun JO,  

[Date]2012/10/11
[Paper #]VLD2012-48,SIP2012-70,ICD2012-65,IE2012-72
A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage

Gong CHEN,  Yu ZHANG,  Qing DONG,  Shigetoshi NAKATAKE,  Bo YANG,  Jing LI,  

[Date]2012/10/11
[Paper #]VLD2012-49,SIP2012-71,ICD2012-66,IE2012-73
Development of Heterogeneous Multi-Core SoC Visconti^2 for Image Recognition Applications

Takashi MIYAMORI,  Yasuki TANABE,  Moriyasu BANNO,  

[Date]2012/10/11
[Paper #]VLD2012-50,SIP2012-72,ICD2012-67,IE2012-74
Accelerator Architecture for Multi Scale Filter Operation

Shinya UENO,  ERIC Gauthier LOVIC,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2012/10/11
[Paper #]VLD2012-51,SIP2012-73,ICD2012-68,IE2012-75
Load buffer with conversion capability from tiled data to raster data for motion search

Takumi Inomata,  Atsushi Tachino,  Takahiro Sasaki,  Kazuhiko Ohno,  Toshio Kondo,  

[Date]2012/10/11
[Paper #]VLD2012-52,SIP2012-74,ICD2012-69,IE2012-76
A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A^2BC) Motion Estimation Algorithm

Tadayoshi Enomoto,  Nobuaki Kobayashi,  

[Date]2012/10/11
[Paper #]VLD2012-53,SIP2012-75,ICD2012-70,IE2012-77
CMOS Op-amp Circuit Synthesis with Geometric Programming

Yu ZHANG,  Qing DONG,  Shigetoshi NAKATAKE,  Bo YANG,  Jing LI,  

[Date]2012/10/11
[Paper #]VLD2012-54,SIP2012-76,ICD2012-71,IE2012-78
Fast Estimation of Dynamic Delay Distribution

Dai AKITA,  Kenta ANDO,  Atsushi TAKAHASHI,  

[Date]2012/10/11
[Paper #]VLD2012-55,SIP2012-77,ICD2012-72,IE2012-79
Reduction of array accesses with WAR dependencies

Takayuki OOKAWA,  Kenshu SETO,  

[Date]2012/10/11
[Paper #]VLD2012-56,SIP2012-78,ICD2012-73,IE2012-80
Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit

Yuta ATOBE,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2012/10/11
[Paper #]VLD2012-57,SIP2012-79,ICD2012-74,IE2012-81
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