Engineering Sciences/NOLTA-Reliability(Date:2020/11/17)

Presentation
Power Analysis Based on Probability Calculation of Small Regions in LSI

Ryo Oba(Kyutech),  Ryu Hoshino(Kyutech),  Kohei Miyase(Kyutech),  Xiaoqing Wen(Kyutech),  Seiji Kajihara(Kyutech),  

[Date]2020-11-17
[Paper #]VLD2020-13,ICD2020-33,DC2020-33,RECONF2020-32
Analysis of Resistance Distribution in Chips with Inductive Coupling Wireless Communication Interface

Hideto Kayashima(Keio Univ.),  Hideharu Amano(Keio Univ.),  Tsunaaki Shidei(Keio Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-19,ICD2020-39,DC2020-39,RECONF2020-38
[Keynote Address] Prospect of Large-Scale Neural-Network Simulation by Exa-scale Computing

Jun Igarashi(RIKEN),  

[Date]2020-11-17
[Paper #]
Quantum Circuit Design by Steiner-Gauss with Considering the Order of Qubits

Zhengtong Han(Ritsumei Univ.),  Shigeru Yamashita(Ritsumei Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-23,ICD2020-43,DC2020-43,RECONF2020-42
Design of Nonvolatile SRAM Using SONOS Flash Cell and its Evaluation by Circuit Simulation

Takaki Urabe(KIT),  Koji Nii(KIT),  Kazutoshi Kobayashi(KIT),  

[Date]2020-11-17
[Paper #]VLD2020-11,ICD2020-31,DC2020-31,RECONF2020-30
DET Flip-Flops with SEU Detection Capability Using DICE and C-Element

Xu Haijia(Chiba Univ.),  Kazuteru Namba(Chiba Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-14,ICD2020-34,DC2020-34,RECONF2020-33
Efficient computation of inductive invariant through flipflop selection

Fudong Wang(U-Tokyo),  Masahiro Fujita(U-Tokyo),  

[Date]2020-11-17
[Paper #]VLD2020-20,ICD2020-40,DC2020-40,RECONF2020-39
R-GCN Based Function Inference for An Arithmetic Circuit

Yuichiro Fujishiro(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Hiroto Ito(MITSUBISHI ELECTRIC ENGINEERING),  Daisuke Ido(MITSUBISHI ELECTRIC ENGINEERING),  

[Date]2020-11-17
[Paper #]VLD2020-21,ICD2020-41,DC2020-41,RECONF2020-40
A Study on Power Gating Switch Control Technique for Nonvolatile Logic LSI

Fangcen Zhong(Tohoku Univ.),  Masanori Natsui(Tohoku Univ.),  Takahiro Hanyu(Tohoku Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-12,ICD2020-32,DC2020-32,RECONF2020-31
PID制御システムの異種冗長設計における高位設計手法の提案と評価

Taichi Saikai(Nagasaki Univ.),  Koyoko Miyata(Nagasaki Univ.),  Taito Manabe(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-16,ICD2020-36,DC2020-36,RECONF2020-35
Restricted-Area and Fast Sample Preparation of a Fluid using Programmable Microfluidic Devices

Ou Suiketsu(Ritsumei Univ.),  Yamashita Shigeru(Ritsumei Univ.),  Sudip Roy(Indian Institute of Technology (IIT) Roorkee),  Juinn-Dar Huang(National Chiao Tung University),  

[Date]2020-11-17
[Paper #]VLD2020-25,ICD2020-45,DC2020-45,RECONF2020-44
Implementation of YOLO in the AI accelerator ReNA

Toma Uemura(Kumamoto Univ.),  Yasuhiro Nakahara(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masato Kiyama(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-22,ICD2020-42,DC2020-42,RECONF2020-41
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder

Naoto Soga(Tokyo Tech),  Shimpei Sato(Tokyo Tech),  HIroki Nakahara(Tokyo Tech),  

[Date]2020-11-17
[Paper #]VLD2020-17,ICD2020-37,DC2020-37,RECONF2020-36
Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits

Ryosuke Matsuo(Kyoto Univ),  Shin-ichi Minato(Kyoto Univ),  

[Date]2020-11-17
[Paper #]VLD2020-24,ICD2020-44,DC2020-44,RECONF2020-43
Transformation of Mixing Graphs Considering Splitting Errors on Digital Microfluidic Biochip

Ikuru Yoshida(Ritsumeikan Univ.),  Shigeru Yamashita(Ritsumeikan Univ.),  

[Date]2020-11-17
[Paper #]VLD2020-26,ICD2020-46,DC2020-46,RECONF2020-45
次世代ALICE TPCむけデータ収集システムにおけるクラスタ検出アルゴリズムのFPGA実装の検討

Taisei Imahigashi(Univ. Ryukyus),  Sharma Samarth(NIAS),  Daniel Goh Jia Qin(NIAS),  Yuki Matsuyama(NIAS),  Masanori Ogino(NIAS),  Ken Oyama(NIAS),  Hiroyuki sako(JAEA),  Taku Gunji(Univ. of Tokyo),  Yasunori Osana(Univ. Ryukyus),  

[Date]2020-11-17
[Paper #]VLD2020-18,ICD2020-38,DC2020-38,RECONF2020-37
Control Point Selection Approach for Scan Pattern Reduction under Multi-cycle Test

Hikaru Tamaki(Ehime Univ.),  Senling Wang(Ehime Univ.),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  Hiroyuki Iwata(Renesas),  Yoichi Maeda(Renesas),  Jun Matsushima(Renesas),  

[Date]2020-11-17
[Paper #]VLD2020-15,ICD2020-35,DC2020-35,RECONF2020-34
[Keynote Address] Quality Assurances of the Fugaku Supercomputer: Function, Performance and Power

Takahide Yoshikawa(FLAB),  

[Date]2020-11-18
[Paper #]VLD2020-36,ICD2020-56,DC2020-56,RECONF2020-55
Column-Parallel Pipelined ADC with Ring Amplifier for High Speed and High Spatial Resolution CMOS Image Sensor

Takashi Kojima(TUS),  Toshinori Otaka(*),  Yusuke Kameda(TUS),  Takayuki Hamamoto(TUS),  

[Date]2020-11-18
[Paper #]VLD2020-28,ICD2020-48,DC2020-48,RECONF2020-47
Physically Unclonable Functions(PUF) curcuit using Non-Volatile Flip-Flop and security evaluation against modeling attacks

Hiroki Ishihara(Shibaura IT),  Kimiyoshi Usami(Shibaura IT),  

[Date]2020-11-18
[Paper #]VLD2020-37,ICD2020-57,DC2020-57,RECONF2020-56
12>> 1-20hit(29hit)