IEICE Technical Committee

Engineering Sciences/NOLTA-Reliability(Date:2018/12/05)

Presentation

A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones

Yusuke Funabashi(Ritsumeikan Univ.), Atsuya Shibata(Ritsumeikan Univ.), Shunsuke Negoro(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2018-12-05
[Paper #]VLD2018-41,DC2018-27

Basic Evaluation of Netlist Function Inference using GCN

Hiroki Oyama(kumamoto Univ.), Motoki Amagasaki(kumamoto Univ.), Masahiro Iida(kumamoto Univ.), Hiroaki Yasuda(MITSUBISHI ELECTRIC ENGINEERING), Hiroto Ito(MITSUBISHI ELECTRIC ENGINEERING),

[Date]2018-12-05
[Paper #]VLD2018-44,DC2018-30

Improved Routing Method for Two Layer Self-Aligned Double Patterning

Shoya Tamura(TUAT), Kunihiro Fujiyoshi(TUAT),

[Date]2018-12-05
[Paper #]VLD2018-45,DC2018-31

Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA

Kotaro Tamura(UEC univ.), Tetsu Narumi(UEC univ.),

[Date]2018-12-05
[Paper #]RECONF2018-34

Design Automation and Optimal Architecture of NLoC

Yuto Umeda(Ritsumeikan Univ.), Shigeru Yamashita(Ritsumeikan Univ.),

[Date]2018-12-05
[Paper #]VLD2018-40,DC2018-26

Horizontal Wireless Bus for Free-Form SiP

Junichiro Kadomoto(The Univ. of Tokyo), Hidetsugu Irie(The Univ. of Tokyo), Shuichi Sakai(The Univ. of Tokyo),

[Date]2018-12-05
[Paper #]VLD2018-46,DC2018-32

An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL

Youki Sada(titech), Masayuki Shimoda(titech), Shimpei Sato(titech), Hiroki Nakahara(titech),

[Date]2018-12-05
[Paper #]RECONF2018-35

Prototyping of Real-time Computer-Aided Diagnosis System for Colorectal Endoscopic Movies and Images with Machine Learning

Takumi Okamoto(Hiroshima Univ.), Masayuki Odagawa(Hiroshima Univ.), Koujiroh Takebayashi(Hiroshima Univ.), Mikihisa Nagano(Hiroshima Univ.), Tetsushi Koide(Hiroshima Univ.), Toru Tamaki(Hiroshima Univ.), Bisser Raytchev(Hiroshima Univ.), Kazufumi Kaneda(Hiroshima Univ.), Shigeto Yoshida(JR Hiroshima Hospital), Hiroshi Mieno(JR Hiroshima Hospital), Shinji Tanaka(Hiroshima Univ.), Takayuki Sugawara(Cadence, Japan), Hiroshi Toishi(Cadence, Japan), Masayuki Tsuji(Cadence, Japan), Nobuo Tamba(Cadence, Japan),

[Date]2018-12-05
[Paper #]VLD2018-42,DC2018-28

［基調講演］畳込みニューラルネットワークの専用ハードウェアに関する研究動向

Hiroki Nakahara(Titech),

[Date]2018-12-05
[Paper #]VLD2018-43,CPM2018-87,ICD2018-48,IE2018-66,CPSY2018-36,DC2018-29,RECONF2018-36

[Keynote Address] Challenge of Post CMOS Circuit Technologies for AI Hardware

Takahiro Hanyu(Tohoku Univ.),

[Date]2018-12-05
[Paper #]

Malleable Task Scheduling for Energy Minimization on Heterogeneous Multicores

Hiroki Nishikawa(Ritsumeikan Univ.), Kana Shimada(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2018-12-06
[Paper #]VLD2018-63,DC2018-49

Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD

Hidehito Fujiishi(Hiroshima city Univ.), Tokio Kamada(Hiroshima city Univ.), Tetsuo Hironaka(Hiroshima city Univ.), Kazuya Tanigawa(Hiroshima city Univ.), Atsushi Kubota(Hiroshima city Univ.),

[Date]2018-12-06
[Paper #]VLD2018-48,DC2018-34

Secure PUF Authentication Method against Machine Learning Attack

Yusuke Nozaki(Meijo Univ.), Masaya Yoshikawa(Meijo Univ.),

[Date]2018-12-06
[Paper #]VLD2018-49,DC2018-35

Communication-Aware Scheduling for Data-Parallel Tasks

Kana Shimada(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2018-12-06
[Paper #]VLD2018-64,DC2018-50

A Case Study on Memory Architecture Exploration for FPGA-based Manycores

Seiya Shirakuni(Ritsumeikan Univ.), Ittetsu Taniguchi(Osaka Univ.), Hiroyuki Tomiyama(Ritsumeikan Univ.),

[Date]2018-12-06
[Paper #]VLD2018-53,DC2018-39

An Approach for Reliability Improvement of Memristor-based Neural Network through Weight Prediction

Mamoru Ishizaka(NAIST), Michihiro Shintani(NAIST), Michiko Inoue(NAIST),

[Date]2018-12-06
[Paper #]VLD2018-50,DC2018-36

Improved Thread Execution for GPU-oriented OpenCL Programs on Multicore Processors

Takafumi Miyazaki(Ritsumeikan Univ), Hayato Hidari(Ritsumeikan Univ), Naohisa Hojo(Ritsumeikan Univ), Naohisa Hojo(Osaka Univ), Hiroyuki Tomiyama(Ritsumeikan Univ),

[Date]2018-12-06
[Paper #]VLD2018-54,DC2018-40

Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC

Satoshi Hirai(Tokushima Univ.), Hiroyuki Yotsuyanagi(Tokushima Univ.), Masaki Hashizume(Tokushima Univ.),

[Date]2018-12-06
[Paper #]VLD2018-56,DC2018-42

Design method of millimeter wave CMOS amplifier circuit with flat frequency characteristics

Shota Kohara(Hiroshima Univ.), Shuhei Amakawa(Hiroshima Univ.), Takeshi Yoshida(Hiroshima Univ.), Minoru Fujishima(Hiroshima Univ.),

[Date]2018-12-06
[Paper #]CPM2018-90,ICD2018-51,IE2018-69

Study on the Applicability of ATPG Pattern for DFT Circuit

Kohki Taniguchi(Tokushima Univ.), Hiroyuki Yotsuyanagi(Tokushima Univ.), Masaki Hashizume(Tokushima Univ.),

[Date]2018-12-06
[Paper #]VLD2018-58,DC2018-44