Engineering Sciences/NOLTA-Reliability(Date:2018/03/07)

Presentation
Minimizing End-to-end Latency in Circuit-switched Network for Parallel Computers

Yao Hu(NII),  Shoichi Hirasawa(NII),  Michihiro Koibuchi(NII),  

[Date]2018-03-07
[Paper #]CPSY2017-135,DC2017-91
Design and Implementation of A Critical Path Monitor for Adaptive Voltage Scaling

Ryosuke Kazami(Keio Univ.),  Hayate Okuhara(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2018-03-07
[Paper #]CPSY2017-139,DC2017-95
Optimization of Memory Accesses of Large Scale Graph Analysis Using Multiport and Multibank Memory

Keigo Teramoto(Hiroshima City Univ.),  Atsushi Kubota(Hiroshima City Univ.),  Tetsuo Hironaka(Hiroshima City Univ.),  

[Date]2018-03-07
[Paper #]CPSY2017-136,DC2017-92
Calculation method for double-precision floating-point sine and cosine functions on an FPGAs

Yukio Toyoshima(Kyoto Univ.),  Naofumi Takagi(Kyoto Univ.),  

[Date]2018-03-07
[Paper #]CPSY2017-138,DC2017-94
FPGAを対象としたC-to-OpenCLトランスレータの自動最適化機能の検討

Daichi Ishizaki(Hiroshima City Univ.),  Yoshiki Ebisuhama(Hiroshima City Univ.),  Atsushi Kubota(Hiroshima City Univ.),  Kazuya Tanigawa(Hiroshima City Univ.),  Tetsuo Hironaka(Hiroshima City Univ.),  

[Date]2018-03-07
[Paper #]CPSY2017-134,DC2017-90
高抽象度言語とオートチューニング機能を持つ動画像処理環境

Kazuki Furuhashi(Nagoya Inst. of Tech.),  Tomoaki Tsumura(Nagoya Inst. of Tech.),  

[Date]2018-03-07
[Paper #]CPSY2017-133,DC2017-89
A System for Analyzing Memory Snapshot with NVDIMM

Masahito Misu(UEC),  Shinobu Miwa(UEC),  Hayato Yamaki(UEC),  Hiroki Honda(UEC),  

[Date]2018-03-07
[Paper #]CPSY2017-137,DC2017-93
Implementation GoogLeNet on multi FPGAs

Kensuke Iizuka(Keio Univ),  Kazusa Musha(Keio Univ),  Hideharu Amano(Keio Univ),  

[Date]2018-03-08
[Paper #]CPSY2017-141,DC2017-97
Design of Memoristor-Logic-Based Check Correction Code Circuit

Mamoru Ishizaka(NITNC),  Michihiro Shintani(NAIST),  Michiko inoue(NAIST),  

[Date]2018-03-08
[Paper #]CPSY2017-146,DC2017-102
A Note On Privacy Preserving k-Nearest Neighbors Algorithms

Yuya Fukuchi(TMU),  Kazuya Sakai(TMU),  Satoshi Fukumoto(TMU),  

[Date]2018-03-08
[Paper #]CPSY2017-147,DC2017-103
Design of Context Cache on IO Core Processor for Embedded Real-Time Systems

So Haramura(Keio Univ.),  Haruki Shishido(Keio Univ.),  Nobuyuki Yamasaki(Keio Univ.),  

[Date]2018-03-08
[Paper #]CPSY2017-143,DC2017-99
Design of time synchronization scheme using Responsive Link

Yuta Tsukahara(Keio Univ.),  Nobuyuki Yamasaki(Keio Univ.),  

[Date]2018-03-08
[Paper #]CPSY2017-144,DC2017-100
IPC Control Unit for Fluid Scheduling

Masaki Takeuchi(Keio Univ.),  Nobuyuki Yamasaki(Keio Univ.),  

[Date]2018-03-08
[Paper #]CPSY2017-145,DC2017-101
Development of Attaching Security Enhancement Device

Kenji Toda(AIST),  Kazukuni Kobara(AIST),  Hirofumi Sakane(AIST),  

[Date]2018-03-08
[Paper #]CPSY2017-150,DC2017-106
A Study of Kernel Clustering for Reducing Memory Footprint of CNN

Yuki Matsui(UEC),  Shinobu Miwa(UEC),  Satoshi Shindo(NITech),  Tomoaki Tsumura(NITech),  Hayato Yamaki(UEC),  Hiroki Honda(UEC),  

[Date]2018-03-08
[Paper #]CPSY2017-140,DC2017-96
Selecting a Rule Set of the Logical Inference System with Machine Learning

Shozo Takeoka(TUAT),  Tomoaki Shikina(TUAT),  Hironori Nakajo(TUAT),  

[Date]2018-03-08
[Paper #]CPSY2017-142,DC2017-98
Implementation of Ack Authentication in Wireless Sensor Networks

Takashi Minohara(Takushoku Univ.),  Wenyang Wang(Takushoku Univ.),  

[Date]2018-03-08
[Paper #]CPSY2017-149,DC2017-105
A Study of Response Time Analysis of Controller Area Networks

Ryouhei Satoh(Tokyo Metropolitan Univ.),  Kazuya Sakai(Tokyo Metropolitan Univ.),  Satoshi Fukumoto(Tokyo Metropolitan Univ.),  Mamoru Ohara(Tokyo Metropolitan Univ.),  Masayuki Arai(Nihon Univ.),  

[Date]2018-03-08
[Paper #]CPSY2017-148,DC2017-104